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1.
公开(公告)号:US11721389B2
公开(公告)日:2023-08-08
申请号:US17948057
申请日:2022-09-19
发明人: Toshiyuki Sato , Hidekazu Noguchi
IPC分类号: G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/406 , G11C11/4076
CPC分类号: G11C11/4091 , G11C11/4074 , G11C11/4087 , G11C11/40611 , G11C11/4076
摘要: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.
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2.
公开(公告)号:US20230013417A1
公开(公告)日:2023-01-19
申请号:US17948057
申请日:2022-09-19
发明人: Toshiyuki Sato , Hidekazu Noguchi
IPC分类号: G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/406
摘要: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.
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公开(公告)号:US11176977B2
公开(公告)日:2021-11-16
申请号:US17183604
申请日:2021-02-24
IPC分类号: G11C8/08 , G11C29/02 , G11C11/408 , G11C29/12
摘要: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
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公开(公告)号:US10854273B1
公开(公告)日:2020-12-01
申请号:US16450737
申请日:2019-06-24
发明人: Toshiyuki Sato
IPC分类号: G11C8/00 , G11C11/408 , G11C8/10 , G11C8/08
摘要: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
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公开(公告)号:US20190074834A1
公开(公告)日:2019-03-07
申请号:US16183615
申请日:2018-11-07
发明人: Toshiyuki Sato
IPC分类号: H03K19/00 , H01L23/522
摘要: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad included in a pad formation area that receives a power voltage; a sub-threshold current reduction circuit (SCRC) included in a peripheral circuit area including a via disposed on a first side of the peripheral circuit area, and a wiring that couples the pad to the via. The SCRC further includes: a voltage line coupled to the via; a logic gate circuit that propagates a signal; an SCRC voltage line coupled to the logic gate circuit; and a SCRC switch disposed in proximity to the via and couples the SCRC voltage line to the voltage line.
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公开(公告)号:US20230317139A1
公开(公告)日:2023-10-05
申请号:US17711858
申请日:2022-04-01
发明人: Toshiyuki Sato
IPC分类号: G11C11/408 , G11C11/4076
CPC分类号: G11C11/4085 , G11C11/4076 , G11C11/4087
摘要: An apparatus includes a subword driver configured to drive a subword line, wherein the subword driver includes a transistor coupled to the subword line, a word driver control circuit configured to provide a first control signal and a second control signal, and a word driver configured to receive the first and second control signals, and based on the first control signal provide a driving signal including a plurality of reset pulses to the transistor of the subword driver to activate the transistor a corresponding plurality of times to discharge the subword line, and further provide the driving signal including a transition following the plurality of reset pulses to activate the transistor to further discharge the subword line.
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公开(公告)号:US20210356520A1
公开(公告)日:2021-11-18
申请号:US16874562
申请日:2020-05-14
发明人: Toshiyuki Sato
IPC分类号: G01R31/3177 , G01R31/317
摘要: Semiconductor devices that include test circuitry to measure internal signal wire propagation delays during memory access operations, and circuity configured to store delay information that is used to configure internal delays based on the measured internal signal propagation circuit delays. The semiconductor device includes a test circuit configured to measure a signal propagation delay between a command decoder and a bank logic circuit based on time between receipt of a test command signal directly from the command decoder and a time of receipt of the test command signal routed through the bank logic circuit.
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公开(公告)号:US11990175B2
公开(公告)日:2024-05-21
申请号:US17711858
申请日:2022-04-01
发明人: Toshiyuki Sato
IPC分类号: G11C11/00 , G11C11/4076 , G11C11/408
CPC分类号: G11C11/4085 , G11C11/4076 , G11C11/4087
摘要: An apparatus includes a subword driver configured to drive a subword line, wherein the subword driver includes a transistor coupled to the subword line, a word driver control circuit configured to provide a first control signal and a second control signal, and a word driver configured to receive the first and second control signals, and based on the first control signal provide a driving signal including a plurality of reset pulses to the transistor of the subword driver to activate the transistor a corresponding plurality of times to discharge the subword line, and further provide the driving signal including a transition following the plurality of reset pulses to activate the transistor to further discharge the subword line.
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公开(公告)号:US20210183422A1
公开(公告)日:2021-06-17
申请号:US17183604
申请日:2021-02-24
IPC分类号: G11C8/08 , G11C29/02 , G11C11/408
摘要: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
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10.
公开(公告)号:US11450378B2
公开(公告)日:2022-09-20
申请号:US17037467
申请日:2020-09-29
发明人: Toshiyuki Sato , Hidekazu Noguchi
IPC分类号: G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/406 , G11C11/4076
摘要: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.
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