公开(公告)号：US20240312529A1

公开(公告)日：2024-09-19

申请号：US18602960

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Karan Banerjee ,  Waing Pyie Soe ,  Shyam Sunder Raghunathan

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/08

Abstract: Control logic in a memory device receives a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of a memory array of a memory device and determines whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state. Responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state, the control logic identifies a partial block read voltage offset value and causes a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline.