公开(公告)号：US20210065789A1

公开(公告)日：2021-03-04

申请号：US16552108

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Kowles ,  Kevin R. Brandt

IPC: G11C11/56 ,  G11C16/34 ,  G06F11/10 ,  G11C29/12

Abstract: An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

公开(公告)号：US12061543B2

公开(公告)日：2024-08-13

申请号：US17702305

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Kowles

IPC: G06F12/0804 ,  G11C29/44

CPC classification number: G06F12/0804 ,  G11C29/44 ,  G06F2212/1032

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

公开(公告)号：US20240394185A1

公开(公告)日：2024-11-28

申请号：US18793458

申请日：2024-08-02

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Kowles

IPC: G06F12/0804 ,  G11C29/44

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

公开(公告)号：US20220214970A1

公开(公告)日：2022-07-07

申请号：US17702305

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Kowles

IPC: G06F12/0804 ,  G11C29/44

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

公开(公告)号：US11112979B2

公开(公告)日：2021-09-07

申请号：US16523615

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Woei Chen Peh ,  Eng Hong Tan ,  Andrew M. Kowles ,  Xiaoxin Zou ,  Zaihas Amri Fahdzan Bin Hasfar

IPC: G06F3/06

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks. After the memory condition has been met, the memory resources of the memory sub-system are then allocated by erase group according to a second set of criteria, wherein the second set of criteria allocates the memory resources irrespective of bad block association for each erase group after the determining that the memory condition has been met.

公开(公告)号：US20210026547A1

公开(公告)日：2021-01-28

申请号：US16523615

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Woei Chen Peh ,  Eng Hong Tan ,  Andrew M. Kowles ,  Xiaoxin Zou ,  Zaihas Amri Fahdzan Bin Hasfar

IPC: G06F3/06

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks. After the memory condition has been met, the memory resources of the memory sub-system are then allocated by erase group according to a second set of criteria, wherein the second set of criteria allocates the memory resources irrespective of bad block association for each erase group after the determining that the memory condition has been met.

公开(公告)号：US10725912B2

公开(公告)日：2020-07-28

申请号：US16226282

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Kowles

IPC: G06F12/0804 ,  G11C29/44

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

公开(公告)号：US11914474B2

公开(公告)日：2024-02-27

申请号：US18167992

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Andrew M. Kowles ,  Adam J. Hieb

IPC: G06F11/07 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

公开(公告)号：US20230195572A1

公开(公告)日：2023-06-22

申请号：US18167992

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Andrew M. Kowles ,  Adam J. Hieb

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

公开(公告)号：US11301381B2

公开(公告)日：2022-04-12

申请号：US16912318

申请日：2020-06-25

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Kowles

IPC: G06F12/0804 ,  G11C29/44

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.