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    Techniques for controlling command order
    1.
    发明授权
    Techniques for controlling command order 有权

    公开(公告)号：US12282684B2

    公开(公告)日：2025-04-22

    申请号：US17654536

    申请日：2022-03-11

    Applicant: Micron Technology, Inc.

    Inventor： Christian M. Gyllenskog ,  Luca Porzio

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for techniques for controlling command order are described. An entity of a host system, such as a file system, may insert a sequential identifier into commands generated by the entity to indicate an order of the commands. In some examples, the host system may specify a set of commands in a first sequence to be transmitted to the memory system. The host system may subsequently reorder the set of commands in to a second sequence and transmit the set of commands to the memory system. In some cases, following a power-on condition, the memory system may determine a latest valid command of the set of commands. The memory system may subsequently invalidate one or more logical addresses associated with commands having sequence identifiers after the sequence identifier of the latest valid command.

    Reading sequential data using mapping information stored at a host device
    3.
    发明授权
    Reading sequential data using mapping information stored at a host device 有权

    公开(公告)号：US11966632B2

    公开(公告)日：2024-04-23

    申请号：US17556066

    申请日：2021-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Roberto Izzi ,  Nicola Colella ,  Luca Porzio ,  Marco Onorato

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

    Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

    Write booster buffer and hibernate
    4.
    发明授权
    Write booster buffer and hibernate 有权

    公开(公告)号：US11934692B2

    公开(公告)日：2024-03-19

    申请号：US17645265

    申请日：2021-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Deping He

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.

    TECHNIQUES FOR PRIORITY INFORMATION
    5.
    发明公开
    TECHNIQUES FOR PRIORITY INFORMATION 审中-公开

    公开(公告)号：US20240061605A1

    公开(公告)日：2024-02-22

    申请号：US17888982

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Gianluca Coppola ,  Ryan Laity ,  Christopher Joseph Bueb

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for techniques for priority information are described. A memory system may be configured to receive, at a memory system, an indication that data is critical to operating the memory system; receive the data that is critical to operating the memory system based at least in part on the indication; select one more parameters to provide a reliability of a storage of the data into a memory device of the memory system based at least in part on receiving the indication and receiving the data; and program the data into the memory device of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.

    PRIORITIZATION OF BACKGROUND MEDIA MANAGEMENT OPERATIONS IN MEMORY SYSTEMS
    6.
    发明公开
    PRIORITIZATION OF BACKGROUND MEDIA MANAGEMENT OPERATIONS IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20230401007A1

    公开(公告)日：2023-12-14

    申请号：US18199057

    申请日：2023-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Ciro Feliciano

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246

    Abstract: Described are systems and methods for prioritization of background media management operations in memory systems. An example system comprises a controller coupled to a memory array comprising a plurality of memory cells. The controller is configured to perform operations, comprising: identifying a plurality of address ranges referencing respective sets of memory cells of the memory array, wherein each address range is associated with a respective memory access operation counter reflecting a number of memory access operations that have been performed with respect to a corresponding set of memory cells; identifying, among the plurality of address ranges, an address range associated with a maximum value of a corresponding memory access operation counter; and causing a media management operation to be performed with respect to a set of memory cells referenced by the identified address range.

    TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS
    7.
    发明公开
    TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS 审中-公开

    公开(公告)号：US20230384972A1

    公开(公告)日：2023-11-30

    申请号：US17752354

    申请日：2022-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Roberto Izzi ,  Luca Porzio ,  Marco Onorato

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

    Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

    COMMANDED DEVICE STATES FOR A MEMORY SYSTEM
    8.
    发明公开
    COMMANDED DEVICE STATES FOR A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230376205A1

    公开(公告)日：2023-11-23

    申请号：US17663722

    申请日：2022-05-17

    Applicant: Micron Technology, Inc.

    Inventor： Marco Onorato ,  Luca Porzio ,  Roberto Izzi ,  Nadav Grosz

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

    MEMORY-ALIGNED ACCESS OPERATIONS
    10.
    发明公开
    MEMORY-ALIGNED ACCESS OPERATIONS 审中-公开

    公开(公告)号：US20230195387A1

    公开(公告)日：2023-06-22

    申请号：US18080568

    申请日：2022-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Dionisio Minopoli ,  Olivier Duval

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

    Abstract: Methods, systems, and devices for memory-aligned access operations are described. A target packet size based on a quantity of physical pages addressable by individual first-level pages of a first-level page table for mapping logical address to respective physical pages may be indicated to a host system. A buffer may be configured based on the target packet size and data for an application at the host system and associated with the target packet size may be stored in the buffer. Based on a utilization threshold of the buffer being reached, a set of data stored in the buffer and having the target packet size may be written to a memory device, where a set of physical addresses for storing the set of data may be identified based on a second-level entry of a second-level page.

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