公开(公告)号：US08947965B2

公开(公告)日：2015-02-03

申请号：US13681151

申请日：2012-11-19

Applicant: Micron Technology Inc.

Inventor： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

IPC: G11C11/34 ,  G11C16/26 ,  H01L27/108 ,  H01L29/73 ,  H01L29/78 ,  G11C11/402 ,  H01L27/102

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 所述多个存储单元中的至少一个可以包括耦合到所述阵列的相应位线的第一区域，耦合到所述阵列的相应源极线的第二区域，与所述阵列间隔开并且电容耦合到相应单词的主体区域 阵列的线，其中所述主体区域可以是电浮置的并且设置在所述第一区域和所述第二区域之间，以及耦合到所述阵列的相应载体注入线的第三区域，其中所述相应的载体注入线可以是 阵列中的彼此耦合的多个载流子注入管线。

公开(公告)号：US09064730B2

公开(公告)日：2015-06-23

申请号：US14263780

申请日：2014-04-28

Applicant: Micron Technology, Inc.

Inventor： Wayne Ellis ,  John Kim

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/105 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/1052 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/7841

Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer, an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns, and an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.

Abstract translation: 公开了用于在半导体存储器件中形成与埋入扩散层的接触的技术。 这些技术可以实现为半导体存储器件。 半导体存储器件可以包括衬底，该衬底包括上层，形成在衬底的上层上并以行和列排列的虚拟柱阵列，以及形成在衬底的上层上并且布置在 行和列。 每个虚拟柱可以从上层向上延伸并且具有与衬底的上层电连接的底部接触。 每个有源支柱可以从上层向上延伸，并且具有活动的第一区域，活动的第二区域和活动的第三区域。 每个活性柱也可以与衬底的上层电连接。