公开(公告)号：US20040023452A1

公开(公告)日：2004-02-05

申请号：US10629199

申请日：2003-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L021/8238

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

公开(公告)号：US20030060039A1

公开(公告)日：2003-03-27

申请号：US10263921

申请日：2002-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L021/4763 ,  H01L021/31

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract translation: 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 通常，钝化层包括SixOyNz。

公开(公告)号：US20040159895A1

公开(公告)日：2004-08-19

申请号：US10780014

申请日：2004-02-17

Applicant: Micron Technology, Inc.

Inventor： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

IPC: H01L029/76 ,  H01L021/336

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

Abstract translation: 该方法包括在衬底之上形成由BPSG组成的层和多个晶体管，在BPSG层上形成电介质层，介电层由介电常数大于约6.0的材料构成，形成多个开口 电介质层和BPSG层，每个开口允许接触晶体管之一的掺杂区域，并且在每个开口中形成导电局部互连。 在另一实施例中，该方法包括在衬底之上和晶体管之间形成由BPSG组成的层，在形成在BPSG层中的开口中形成局部互连，在局部互连形成之后减小BPSG层的厚度，并形成 电介质层在BPSG层之上和局部互连之间，其中介电层具有大于约6.0的介电常数。

公开(公告)号：US20030234422A1

公开(公告)日：2003-12-25

申请号：US10175774

申请日：2002-06-20

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Zhongze Wang

IPC: H01L027/108 ,  H01L029/76 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

Abstract: The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

Abstract translation: 本发明提供了一种制造MOSFET中的电介质塞的技术。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域 和漏区。

公开(公告)号：US20030153155A1

公开(公告)日：2003-08-14

申请号：US10073723

申请日：2002-02-11

Applicant: Micron Technology Inc.

Inventor： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

IPC: H01L021/8238 ,  H01L021/336

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L29/0653

Abstract: Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.

Abstract translation: 场效应晶体管及其制造方法具有与其源/漏区分开形成的沟道区，并且具有介于沟道区和源/漏区之间的单晶材料。 单晶材料包括单晶硅和硅 - 锗合金。

公开(公告)号：US20040229414A1

公开(公告)日：2004-11-18

申请号：US10758059

申请日：2004-01-15

Applicant: Micron Technology, Inc.

Inventor： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

IPC: H01L021/00

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L29/0653

Abstract: A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.

Abstract translation: 场效应晶体管具有体半导体衬底中的沟道区，沟道区的第一侧上的第一源极/漏极区，沟道区的第二侧上的第二源极/漏极区和外延的延伸 形成在体半导体衬底上以便从沟道区的每一侧延伸的单晶材料。