公开(公告)号：US20030164513A1

公开(公告)日：2003-09-04

申请号：US10379494

申请日：2003-03-04

Applicant: Micron Technology, Inc.

Inventor： Er-Xuan Ping ,  Jeffrey A. McKee

IPC: H01L029/76

CPC classification number: H01L29/66666 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28562 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/66628 ,  H01L29/66787 ,  H01L29/66893 ,  H01L29/7834 ,  H01L29/78642

Abstract: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface. The resultant structure can function, for example, as a vertical gate of a DRAM cell, elevated source/drain structures, or other semiconductor device feature.

公开(公告)号：US20030153155A1

公开(公告)日：2003-08-14

申请号：US10073723

申请日：2002-02-11

Applicant: Micron Technology Inc.

Inventor： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

IPC: H01L021/8238 ,  H01L021/336

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L29/0653

Abstract: Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.

Abstract translation: 场效应晶体管及其制造方法具有与其源/漏区分开形成的沟道区，并且具有介于沟道区和源/漏区之间的单晶材料。 单晶材料包括单晶硅和硅 - 锗合金。

公开(公告)号：US20030136988A1

公开(公告)日：2003-07-24

申请号：US10338286

申请日：2003-01-08

Applicant: Micron Technology, Inc.

Inventor： Lingyi A. Zheng ,  Er-Xuan Ping

IPC: H01L027/108

CPC classification number: H01L27/10855 ,  H01L28/84 ,  H01L28/91

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection. Thinning of the dielectric layer in turn facilitates higher capacitance values for a given capacitor surface area.

公开(公告)号：US20040183134A1

公开(公告)日：2004-09-23

申请号：US10817175

申请日：2004-03-31

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L029/792

CPC classification number: H01L27/10894 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/933

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

公开(公告)号：US20040185606A1

公开(公告)日：2004-09-23

申请号：US10817704

申请日：2004-03-31

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L021/84 ,  H01L027/12

CPC classification number: H01L27/10894 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/933

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract translation: 本发明包括形成半导体电路的方法。 提供单晶硅衬底，并且形成覆盖衬底的第一部分并且留下未覆盖的第二部分的掩模。 在未覆盖部分中形成沟槽，并且至少部分地填充有半导体材料，该半导体材料包括除硅以外的元素的至少一个原子百分比。 去除掩模，并且在衬底的第一部分上形成第一半导体电路部件。 此外，第二半导体电路部件形成在至少部分地填充沟槽的半导体材料之上。 本发明还包括半导体结构。

公开(公告)号：US20040169259A1

公开(公告)日：2004-09-02

申请号：US10793587

申请日：2004-03-04

Applicant: Micron Technology, Inc.

Inventor： Lingyi A. Zheng ,  Er-Xuan Ping

IPC: H01L027/108

CPC classification number: H01L21/0217 ,  C23C16/0272 ,  C23C16/345 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31051 ,  H01L21/3115 ,  H01L21/3185 ,  H01L21/3211 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract translation: 提供了一种在半导体器件上形成氮化硅膜的方法。 在该方法的一个实施方案中，首先将含硅衬底暴露于二氯硅烷（DCS）和含氮气体的混合物以在表面上沉积薄氮化硅接种层，然后暴露于四氯化硅 （TCS）和包含气体的氮气以在DCS籽晶层上沉积TCS氮化硅层。 在另一个实施方案中，该方法包括在形成DCS氮化物接种层和TCS氮化物层之前首先氮化含硅衬底的表面。 该方法实现了具有足够厚度的TCS氮化物层，以消除起泡和穿通问题，并且不管衬底类型如何，都能提供高电性能。 还提供了形成电容器的方法以及所得到的电容器结构。

公开(公告)号：US20030124799A1

公开(公告)日：2003-07-03

申请号：US10325260

申请日：2002-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Er-Xuan Ping ,  Randhir Thakur

IPC: H01L021/44 ,  H01L021/36 ,  H01L021/8242

CPC classification number: H01L28/84 ,  C23C16/24 ,  C23C16/56 ,  Y10S438/964

Abstract: The present invention provides methods of forming in situ doped rugged silicon and semiconductor devices incorporating conductive rugged silicon. In one aspect, the methods involve forming a layer of amorphous silicon on a substrate at a substantially constant deposition temperature; and converting the layer of amorphous silicon into hemispherical grain silicon by subjecting the layer of amorphous silicon to substantially the deposition temperature while varying pressure.

Abstract translation: 本发明提供了形成原位掺杂的坚固硅和掺入导电坚固硅的半导体器件的方法。 在一个方面，所述方法包括在基本上恒定的沉积温度下在衬底上形成非晶硅层; 以及通过在改变压力的同时使非晶硅层基本上沉积温度来将非晶硅层转变成半球形晶粒硅。

公开(公告)号：US20030098482A1

公开(公告)日：2003-05-29

申请号：US10338287

申请日：2003-01-08

Applicant: Micron Technology, Inc.

Inventor： Lingyi A. Zheng ,  Er-Xuan Ping

IPC: H01L027/108

CPC classification number: H01L27/10855 ,  H01L28/84 ,  H01L28/91

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection. Thinning of the dielectric layer in turn facilitates higher capacitance values for a given capacitor surface area.

公开(公告)号：US20020125508A1

公开(公告)日：2002-09-12

申请号：US10138458

申请日：2002-05-03

Applicant: Micron Technology, Inc.

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L021/8234

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (nullbottom electrodesnull) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract translation: 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US20020079523A1

公开(公告)日：2002-06-27

申请号：US09742748

申请日：2000-12-20

Applicant: Micron Technology, Inc.

Inventor： Lingyi A. Zheng ,  Er-Xuan Ping

IPC: H01L027/108

CPC classification number: H01L27/10855 ,  H01L28/84 ,  H01L28/91

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection. Thinning of the dielectric layer in turn facilitates higher capacitance values for a given capacitor surface area.

Abstract translation: 具有扩散阻挡层的半导体容器电容器结构适用于高密度存储器阵列中，以减少底部电池板和任何底层晶体管对通过周围绝缘材料扩散的物质的损害。 扩散阻挡层可以在包括电容器介电层的预处理，形成和后处理的处理过程中保护底部单元板，任何下层存取晶体管，甚至保护周围绝缘层的表面。 扩散阻挡层抑制或妨碍可能对底板或下面的晶体管（例如含氧物质，含氢物质和/或其它不期望的物质）造成损害的物质的扩散。 扩散阻挡层与电容器介电层分开形成。 这有助于介电层的薄化，因为介电层不需要提供这种扩散保护。 电介质层的薄化又有助于给定电容器表面积的较高的电容值。