公开(公告)号：US11036541B2

公开(公告)日：2021-06-15

申请号：US15875873

申请日：2018-01-19

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aditya Bhandari ,  Bruce J. Sherwin, Jr. ,  Xin David Zhang

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

公开(公告)号：US10599461B2

公开(公告)日：2020-03-24

申请号：US15875922

申请日：2018-01-19

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aditya Bhandari ,  Bruce J. Sherwin, Jr. ,  Xin David Zhang

IPC: G06F12/00 ,  G06F9/455 ,  G06F12/1027 ,  G06F12/1009 ,  G06F21/53 ,  G06F21/79 ,  G06F13/10 ,  G06F12/1036 ,  G06F12/1081 ,  G06F13/28 ,  G06F13/42

Abstract: This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.

公开(公告)号：US11487574B2

公开(公告)日：2022-11-01

申请号：US15875840

申请日：2018-01-19

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aditya Bhandari ,  Bruce J. Sherwin, Jr. ,  Xin David Zhang

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how interrupts may be provided to targeted virtual processors, regardless of where the virtual processors are currently executing. That is, when an interrupt is received, the interrupt may be delivered to a specified virtual processor regardless of which logical processor is currently hosting the virtual processor.

公开(公告)号：US10712766B2

公开(公告)日：2020-07-14

申请号：US15875880

申请日：2018-01-19

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aditya Bhandari ,  Bruce J. Sherwin, Jr. ,  Xin David Zhang

IPC: G06F9/46 ,  G06F1/06 ,  G06F9/455 ,  G06F9/48

Abstract: This disclosure generally relates to time and timer techniques that may be used to virtualize one or more virtual machines. In an example, it may be possible to save and restore a timer of a virtual machine while preserving timer information associated with the timer (e.g., an expiration time, whether the most recent expiration has been signaled, and the enable bit, etc.). For example, a first mode may enable restoring a timer based on a previously-existing enable bit, thereby retaining the state of the timer (e.g., whether the timer is programmed to fire and/or whether the most recent expiration has been signaled). By contrast, a second mode of setting a timer may automatically set the enable bit, thereby automatically enabling the timer to fire, as may be expected by a virtual machine when setting a timer.