SiC semiconductor device comprising a pn junction with a voltage
absorbing edge
    3.
    发明授权
    SiC semiconductor device comprising a pn junction with a voltage absorbing edge 失效
    SiC半导体器件包括具有电压吸收边缘的pn结

    公开(公告)号:US6002159A

    公开(公告)日:1999-12-14

    申请号:US683059

    申请日:1996-07-16

    摘要: A semiconductor component including a silicon carbide substrate. A pn junction includes doped layers of the substrate. The pn junction includes at a surface of the substrate a low doped first conductivity type layer and at a portion of the surface of the substrate a highly doped second conductivity type layer. An edge termination region of the pn junction laterally surrounds the pn junction provided at an edge of at least one of the layers of the pn junction. The edge termination region includes zones of the second conductivity type located at an edge of the highly doped second conductivity type layer. A charge content of the zones decreases toward an edge of the edge termination region in accordance with at least one characteristic selected from the group consisting of a stepwise or continuously decreasing total charge towards an outer border of the edge termination region and a decreasing effective sheet charge density toward an outer border of the edge termination region. An outermost zone of the edge termination region is completely depleted at full design voltage.

    摘要翻译: 包括碳化硅衬底的半导体部件。 pn结包括衬底的掺杂层。 pn结在衬底的表面上包括低掺杂的第一导电类型层,并且在衬底的表面的一部分处包括高度掺杂的第二导电类型层。 pn结的边缘终止区横向地围绕设置在pn结的至少一个层的边缘处的pn结。 边缘终止区域包括位于高度掺杂的第二导电类型层的边缘处的第二导电类型的区域。 根据从边缘终止区域的外边界逐步或连续减小的总电荷和降低的有效片材电荷的组中选出的至少一个特征,区域的电荷含量朝向边缘终止区域的边缘减小 密度朝向边缘终止区域的外边界。 边缘终端区域的最外区域在完全设计电压下完全耗尽。