公开(公告)号：US5967795A

公开(公告)日：1999-10-19

申请号：US520689

申请日：1995-08-30

申请人： Mietek Bakowsky ,  Bo Bijlenga ,  Ulf Gustafsson ,  Christopher Harris ,  Susan Savage

发明人： Mietek Bakowsky ,  Bo Bijlenga ,  Ulf Gustafsson ,  Christopher Harris ,  Susan Savage

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/861 ,  H01L21/20

CPC分类号： H01L29/1608 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/8611 ,  H01L2924/0002 ,  Y10S438/931

摘要： A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards its outermost edge.

摘要翻译： 半导体部件包括pn结，其中pn结的p导电层和n导电层都是掺杂的碳化硅层，并且pn结的至少一个导电层的边缘呈逐步或均匀地减小 总电荷或有效表面电荷密度从在限定的工作结点处的初始值到在从结点的中心部分到其最外边缘的径向方向上的结的最外边缘处的零或几乎为零的总电荷。

公开(公告)号：US5977605A

公开(公告)日：1999-11-02

申请号：US954165

申请日：1997-10-20

申请人： Mietek Bakowsky ,  Bo Bijlenga ,  Ulf Gustafsson ,  Christopher Harris ,  Susan Savage

发明人： Mietek Bakowsky ,  Bo Bijlenga ,  Ulf Gustafsson ,  Christopher Harris ,  Susan Savage

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/1608 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/8611 ,  H01L2924/0002 ,  Y10S438/931

摘要： A semiconductor component, which comprises a pn junction, where both the p-conducting and the n-conducting layers of the pn junction constitute doped silicon carbide layers and where the edge of at least one of the conducting layers of the pn junction, exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

摘要翻译： 一种半导体部件，其包括pn结，其中pn结的p导电层和n导电层都构成掺杂的碳化硅层，并且其中pn结的至少一个导电层的边缘呈现出 在从结合的中心部分到最外边缘的径向方向上，从总限制的工作结点处的初始值逐渐或均匀地减小总电荷或有效表面电荷密度，从而在连接的最外边缘处的零电荷或几乎为零的总电荷 。

公开(公告)号：US6091108A

公开(公告)日：2000-07-18

申请号：US971682

申请日：1997-11-17

申请人： Christopher Harris ,  Bo Bijlenga ,  Lennart Zdansky ,  Ulf Gustafsson ,  Mietek Bakowski ,  Andrey Konstantinov

发明人： Christopher Harris ,  Bo Bijlenga ,  Lennart Zdansky ,  Ulf Gustafsson ,  Mietek Bakowski ,  Andrey Konstantinov

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  H01L29/745

CPC分类号： H01L29/66068 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device of SiC is adapted to hold high voltages in the blocking state thereof. The device comprises two parts (1, 2) each comprising one or more semiconductor layers of SiC and connected in series between two opposite terminals of the device, namely a sub-semiconductor device (1) able to withstand only low voltages in the blocking state thereof and a voltage-limiting part (2) able to withstand high voltages in the blocking state of the device and adapted to protect said sub-semiconductor device by taking a major part of the voltage over the device in the blocking state thereof.

摘要翻译： SiC的半导体器件适于在其阻挡状态下保持高电压。 该器件包括两个部分（1,2），每个部分包括一个或多个SiC半导体层，并且串联连接在器件的两个相对端子之间，即能够仅承受阻塞状态的低电压的子半导体器件（1） 以及能够承受器件的阻断状态下的高电压的电压限制部分（2），并且适用于通过在其阻塞状态下将器件的大部分电压占据主要部分来保护所述次半导体器件。

公开(公告)号：US5786251A

公开(公告)日：1998-07-28

申请号：US678548

申请日：1996-07-09

申请人： Christopher Harris ,  Mietek Bakowski ,  Lennart Zdansky ,  Bo Bijlenga

发明人： Christopher Harris ,  Mietek Bakowski ,  Lennart Zdansky ,  Bo Bijlenga

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7802 ,  Y10S438/931

摘要： In a method for producing a channel region layer in a SiC-layer for providing a voltage-controlled semiconductor device a layer of silicon being one of a) polycrystalline and b) amorphous is applied on top of the SiC-layer, an aperture is etched in the silicon layer extending to the SiC-layer, a surface layer of a certain thickness of the silicon layer is oxidized, and the lateral extension of the channel region layer is determined by removing the oxidized layer and carrying out a further implantation into the area exposed by the so formed enlarged aperture.

摘要翻译： 在用于提供压控半导体器件的SiC层中制造沟道区层的方法中，在SiC层的顶部上施加a）多晶和b）非晶之一的硅层，蚀刻孔 在延伸到SiC层的硅层中，硅层的一定厚度的表面层被氧化，并且通过去除氧化层并进一步注入该区域来确定沟道区域层的横向延伸 被这样形成的扩大的光圈曝光。

公开(公告)号：US5773849A

公开(公告)日：1998-06-30

申请号：US636940

申请日：1996-04-24

申请人： Christopher Harris ,  Mietek Bakowski ,  Ulf Gustafsson ,  Mats Andersson

发明人： Christopher Harris ,  Mietek Bakowski ,  Ulf Gustafsson ,  Mats Andersson

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/749

摘要： A field controlled semiconductor device of SiC has a drain, a highly doped substrate layer on top of the drain and a low doped n-type drift layer on top of the substrate layer. A p-type base layer is located on the drift layer and a vertical trench extends through the base layer. In the trench an n-type channel region extends vertically along a wall of the trench and connects a source region layer to the drift layer. A gate electrode is arranged in the trench to be on the opposite side of the channel region with respect to the base layer.

摘要翻译： SiC的场控半导体器件具有漏极，在漏极顶部具有高度掺杂的衬底层，在衬底层的顶部具有低掺杂的n型漂移层。 p型基层位于漂移层上，垂直沟槽延伸通过基层。 在沟槽中，n型沟道区域沿着沟槽的壁垂直延伸，并将源极区域层连接到漂移层。 沟槽中布置有栅电极，以相对于基层在通道区域的相对侧。

公开(公告)号：US6150671A

公开(公告)日：2000-11-21

申请号：US636943

申请日：1996-04-24

申请人： Christopher Harris ,  Ulf Gustafsson ,  Mietek Bakowski

发明人： Christopher Harris ,  Ulf Gustafsson ,  Mietek Bakowski

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  H01L29/22

CPC分类号： H01L29/7813 ,  H01L29/66068 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  Y10S438/931

摘要： A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.

摘要翻译： 在漏极上形成具有漏极和高掺杂衬底层的SiC晶体管。 可以可选地在衬底层上形成高度n型缓冲层。 在衬底层上形成低掺杂n型漂移层，p型基极层，高掺杂n型源区域层和源极。 具有栅极电极的绝缘层布置在基层的顶部上，并且至少从源极区域基本上横向延伸到n型层。 当向栅电极施加电压时，在p型基极层和绝缘层的界面处，在基极层中基本上横向延伸形成导电反转沟道。 p型基层在与形成反型沟道的绝缘层的界面旁边的区域中低掺杂，并且在漂移层旁边的区域中高度掺杂。

公开(公告)号：US5923051A

公开(公告)日：1999-07-13

申请号：US953420

申请日：1997-10-17

申请人： Christopher Harris ,  Mietek Bakowski ,  Ulf Gustafsson ,  Mats Andersson

发明人： Christopher Harris ,  Mietek Bakowski ,  Ulf Gustafsson ,  Mats Andersson

IPC分类号： H01L21/04 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L31/0312 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7813 ,  H01L29/66068 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7828 ,  H01L29/1608

摘要： A field controlled semiconductor device of SiC comprises superimposed in the order mentioned at least a drain (12), a highly doped substrate layer (1) and a low doped n-type drift layer (2). It has also a highly doped n-type source region layer (6) and a source (11) connected thereto. A doped channel region layer (4) connects the source region layer to the drift layer, and a current is intended to flow therethrough when the device is in an on-state. The device has also a gate electrode (9). The channel region layer has a substantially lateral extension and is formed by a low doped n-type layer (4). The gate electrode (9) is arranged to influence the channel region layer from above for giving a conducting channel (17) created therein from the source region layer to the drift layer a substantially lateral extension.

摘要翻译： SiC的场控半导体器件以至少漏极（12），高度掺杂的衬底层（1）和低掺杂n型漂移层（2）的顺序叠加。 它还具有高掺杂的n型源区域层（6）和与其连接的源极（11）。 掺杂沟道区域层（4）将源区域层连接到漂移层，并且当器件处于导通状态时，电流意图流过其中。 器件还具有栅电极（9）。 沟道区层具有基本上横向的延伸，并由低掺杂n型层（4）形成。 栅电极（9）被布置成从上方影响沟道区域层，以从源极区域向漂移层形成基本上横向延伸的导电沟道（17）。

公开(公告)号：US5909039A

公开(公告)日：1999-06-01

申请号：US783579

申请日：1997-01-13

申请人： Mietek Bakowski ,  Christopher Harris ,  Ulf Gustafsson

发明人： Mietek Bakowski ,  Christopher Harris ,  Ulf Gustafsson

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/74

CPC分类号： H01L29/7396 ,  H01L29/0649

摘要： An IGBT comprises a drain, a highly doped p-type substrate layer, a highly doped n-type buffer layer, a drift layer, a p-type base layer, a highly doped n-type source region layer and a source electrode. A trench is etched in the base layer and an insulating layer with a gate electrode thereon is arranged on the base layer from the source region layer to the drift layer for the creation of a conducting inversion channel there. A contact portion is provided vertically separated from the source region layer and has the source electrode applied thereon for collecting holes injected from the substrate layer to the drift layer at a vertical distance from the source region layer.

摘要翻译： IGBT包括漏极，高掺杂的p型衬底层，高掺杂的n型缓冲层，漂移层，p型基极层，高掺杂的n型源极区域层和源极电极。 在基底层上蚀刻沟槽，并且其上具有栅极电极的绝缘层被布置在从源极区域到漂移层的基底层上，用于在那里形成导电反转通道。 提供了与源区域层垂直分离的接触部分，并且其上施加有源电极，用于从源区域层垂直距离收集从衬底层注入到漂移层的空穴。

公开(公告)号：US5763902A

公开(公告)日：1998-06-09

申请号：US637105

申请日：1996-04-24

申请人： Christopher Harris ,  Ulf Gustafsson ,  Mietek Bakowski

发明人： Christopher Harris ,  Ulf Gustafsson ,  Mietek Bakowski

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/74

CPC分类号： H01L29/6634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7396

摘要： An insulated gate bipolar transistor comprises a drain which supports a highly doped p-type substrate layer; a low doped n-type drift layer supported over the substrate layer; a base layer supported over the drift layer including a trench extending into the base layer, and supporting an insulated gate on an upper surface thereof separated from the trench by a highly doped n-type source region, the trench having a highly doped p-type layer at the bottom thereof vertically separated from the source region; and a source layer disposed over the n-type source region and extending into the trench covering the highly doped p-type layer in the trench bottom, wherein an applied voltage to the gate forms a conducting inversion channel in the base layer for electron transport from the source region to the drain, and the highly doped p-type layer in the bottom of the trench collects holes injected from the substrate layer into the drift layer thereby improving latch up immunity for the transistor.

摘要翻译： 绝缘栅双极晶体管包括支持高掺杂p型衬底层的漏极; 支撑在衬底层上的低掺杂n型漂移层; 支撑在漂移层上的基底层包括延伸到基底层中的沟槽，以及通过高度掺杂的n型源区域在与沟槽分离的上表面上支撑绝缘栅极，该沟槽具有高度掺杂的p型 在与源区垂直分离的底部的层; 以及源极层，设置在n型源极区域上并延伸到覆盖沟槽底部中的高掺杂p型层的沟槽中，其中施加到栅极的电压在基极层中形成用于电子传输的导电反转沟道 到漏极的源极区域和沟槽底部中的高掺杂p型层将从衬底层注入的空穴收集到漂移层中，从而提高晶体管的闭锁抗扰度。

公开(公告)号：US06278133B1

公开(公告)日：2001-08-21

申请号：US09298116

申请日：1999-04-23

申请人： Christopher Harris ,  Andrei Konstantinov ,  Susan Savage

发明人： Christopher Harris ,  Andrei Konstantinov ,  Susan Savage

IPC分类号： H01L310312

CPC分类号： H01L29/0847 ,  G01N27/4143 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/7838

摘要： A field effect transistor of SiC for high temperature application has the source region layer (4), the drain region layer (5) and the channel region layer (6, 7) vertically separated from a front surface (14), where a gate electrode (12) is arranged, for reducing the electric field at said surface in operation of the transistor and in the case of operation as a gas sensor permitting all electrodes except for the gate electrode to be protected from the atmosphere.

摘要翻译： 用于高温施加的SiC的场效应晶体管具有源区域层（4），漏极区域层（5）和沟道区域层（6,7）与前表面（14）垂直分离，其中栅电极 （12）被布置为用于在晶体管的操作中减小所述表面处的电场，并且在作为气体传感器的操作的情况下，允许除了栅电极之外的所有电极被保护免受大气。