公开(公告)号：US20240234228A9

公开(公告)日：2024-07-11

申请号：US18398680

申请日：2023-12-28

Applicant: ROHM CO., LTD.

Inventor： Kunihiro KOMIYA

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0612 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14104 ,  H01L2224/1413 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107

Abstract: The semiconductor device has the CSP structure and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

公开(公告)号：US20240204048A1

公开(公告)日：2024-06-20

申请号：US18082851

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Hwichan Jun

IPC: H01L29/08 ,  H01L23/00 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/0843 ,  H01L24/10 ,  H01L27/085 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L2224/13023

Abstract: Techniques are provided herein to form semiconductor devices having one or more epitaxial source or drain regions wrapped by a conductive contact to form an improved ohmic contact. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between the first source or drain region and a third source or drain region. The first and second semiconductor devices include a subfin region adjacent to a dielectric layer. A conductive layer extends around the first source or drain region such that the conductive layer at least contacts the sidewalls of the first source or drain region and both upper and lower surfaces of the source or drain region. A dielectric layer is also present between the conductive contact and the subfin region.

公开(公告)号：US20240153908A1

公开(公告)日：2024-05-09

申请号：US18204965

申请日：2023-06-02

Applicant: HKC CORPORATION LIMITED

Inventor： Yang PU ,  Haoxuan Zheng

IPC: H01L23/00 ,  H01L25/16 ,  H01L33/38 ,  H01L33/62

CPC classification number: H01L24/81 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L25/167 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/0217 ,  H01L2224/0224 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13016 ,  H01L2224/16145 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/13069 ,  H01L2924/13091

Abstract: A driving substrate, a micro LED transfer device and a micro LED transfer method are provided. A side surface of the driving substrate is arranged with a binding metal layer, a positioning layer is arranged around the binding metal layer, and a width of the positioning layer at a position away from the driving substrate is less than that a width at a position close to the driving substrate.

公开(公告)号：US20240055385A1

公开(公告)日：2024-02-15

申请号：US18315537

申请日：2023-05-11

Applicant: WISTRON NEWEB CORPORATION

Inventor： KUO-HUA HSIEH ,  CHAO-CHIEH CHAN ,  MING-JHE WU ,  CHIH-YANG WENG

IPC: H01L23/00 ,  H01L23/373

CPC classification number: H01L24/17 ,  H01L23/3737 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/10 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/73 ,  H01L2224/11318 ,  H01L2224/10175 ,  H01L2224/1319 ,  H01L2924/0665 ,  H01L2224/13021 ,  H01L2224/14132 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/17517 ,  H01L2224/17051 ,  H01L2224/14152 ,  H01L2224/26175 ,  H01L2224/2731 ,  H01L2224/29021 ,  H01L2224/29013 ,  H01L2224/29012 ,  H01L2224/2919 ,  H01L2224/30155 ,  H01L2224/3015 ,  H01L2224/30051 ,  H01L2224/32237 ,  H01L2224/83007 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/73203

Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.

公开(公告)号：US11901251B2

公开(公告)日：2024-02-13

申请号：US17854316

申请日：2022-06-30

Applicant: ROHM CO., LTD.

Inventor： Kunihiro Komiya

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0612 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/1413 ,  H01L2224/14104 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L24/13 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: The semiconductor device has the CSP structure and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

公开(公告)号：US20240038703A1

公开(公告)日：2024-02-01

申请号：US17878271

申请日：2022-08-01

Applicant: ATI TECHNOLOGIES ULC

Inventor： JIANGUO LI ,  RODEN R. TOPACIO

IPC: H01L23/00

CPC classification number: H01L24/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/05573 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/03334 ,  H01L2224/03849 ,  H01L2224/13007 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/10175

Abstract: A semiconductor device includes a substrate and a conductive pad coupled to the substrate. A first solder mask is coupled to the substrate and to a portion of the conductive pad so the first solder mask covers the portion of the conductive pad and extends above the conductive pad. A second solder mask is coupled to a portion of the first solder mask and extends above the first solder mask.

公开(公告)号：US11855028B2

公开(公告)日：2023-12-26

申请号：US17326941

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Sheng-Pin Yang ,  Hao-Chun Liu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/10 ,  H01L24/17 ,  H01L28/60

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

公开(公告)号：US11837563B2

公开(公告)日：2023-12-05

申请号：US17956768

申请日：2022-09-29

Applicant: InnoLux Corporation

Inventor： Jia-Yuan Chen ,  Tsung-Han Tsai

IPC: H01L23/00 ,  H01L25/13 ,  H01L33/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/24 ,  H01L25/13 ,  H01L33/0095 ,  H01L24/10 ,  H01L2933/0066

Abstract: A method for manufacturing an electronic device includes: providing a substrate; forming a plurality of connecting pads and a plurality of conductive portions partially overlapped by the plurality of connecting pads on the substrate; forming a plurality of conductive lines on the substrate, wherein one of the plurality of conductive lines is partially overlapped with one of the plurality of conductive portions, and an insulating layer is disposed between one of the plurality of connecting pads and the one of the plurality of conductive portions; and bonding a plurality of light emitting units to the plurality of connecting pads.

公开(公告)号：US11700692B2

公开(公告)日：2023-07-11

申请号：US17395893

申请日：2021-08-06

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Akito Yoshida ,  Mahmoud Dreiza ,  Curtis Michael Zwenger

IPC: H05K1/14 ,  H05K3/36 ,  H01L23/31 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H01L21/56 ,  H01L23/498 ,  H05K3/40

CPC classification number: H05K1/14 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/16 ,  H01L24/81 ,  H05K1/11 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K3/303 ,  H05K3/34 ,  H05K3/363 ,  H05K3/4007 ,  H01L23/3171 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/1607 ,  H01L2224/16055 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01079 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/043 ,  Y10T29/49165 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A

公开(公告)号：US10312221B1

公开(公告)日：2019-06-04

申请号：US15844575

申请日：2017-12-17

Applicant: Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

Inventor： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.