公开(公告)号：US20080084766A1

公开(公告)日：2008-04-10

申请号：US11617670

申请日：2006-12-28

申请人： Min Joong Jung ,  Byoung Kwan Jeong ,  Tai Kyu Kang

发明人： Min Joong Jung ,  Byoung Kwan Jeong ,  Tai Kyu Kang

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.

摘要翻译： 闪存器件包括具有多个块的存储单元阵列。 地址寄存器部分被配置为在要擦除的多个块中接收要擦除的第一块的起始块地址和要擦除的多个块中要擦除的最后块的最后块地址。 控制逻辑电路被配置为输出与要擦除的块中的一个对应的擦除命令信号和擦除块地址。 块地址比较部分被配置为将由控制逻辑电路输出的擦除块地址与最后的块地址进行比较，并且基于擦除块地址和最后块地址的比较将控制逻辑电路输出擦除进行信号 。 控制逻辑电路输出要擦除的另一个块的擦除块地址，直到擦除进度信号指示要擦除的最后一个块已经或正被擦除。

公开(公告)号：US07684254B2

公开(公告)日：2010-03-23

申请号：US11617670

申请日：2006-12-28

申请人： Min Joong Jung ,  Byoung Kwan Jeong ,  Tai Kyu Kang

发明人： Min Joong Jung ,  Byoung Kwan Jeong ,  Tai Kyu Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.

摘要翻译： 闪存器件包括具有多个块的存储单元阵列。 地址寄存器部分被配置为在要擦除的多个块中接收要擦除的第一块的起始块地址和要擦除的多个块中要擦除的最后块的最后块地址。 控制逻辑电路被配置为输出与要擦除的块中的一个对应的擦除命令信号和擦除块地址。 块地址比较部分被配置为将由控制逻辑电路输出的擦除块地址与最后的块地址进行比较，并且基于擦除块地址和最后块地址的比较将控制逻辑电路输出擦除进行信号 。 控制逻辑电路输出要擦除的另一个块的擦除块地址，直到擦除进度信号指示要擦除的最后一个块已经或正被擦除。

公开(公告)号：US07609800B1

公开(公告)日：2009-10-27

申请号：US12163910

申请日：2008-06-27

申请人： Sang Oh Lim ,  Byoung Kwan Jeong ,  Mi Sun Yoon

发明人： Sang Oh Lim ,  Byoung Kwan Jeong ,  Mi Sun Yoon

IPC分类号： H03K21/00 ,  H03K23/00

CPC分类号： H03K23/40 ,  H03K23/50

摘要： The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.

摘要翻译： 本发明涉及一种单元计数器块。 根据本发明的一个方面，单元计数器块包括D触发器，第二MUX和第一MUX。 触发器与时钟信号同步地输出第一和第二输出信号。 第二MUX响应于数据负载信号选择D触发器的外部数据和第二输出信号中的任何一个，并输出所选择的信号。 响应于计数器使能信号或数据负载信号，第一MUX将D触发器的第一输出信号和第二MUX的输出信号中的任何一个传送到D触发器的输入信号。

公开(公告)号：US08059460B2

公开(公告)日：2011-11-15

申请号：US12650608

申请日：2009-12-31

申请人： Byoung Kwan Jeong ,  Chul Woo Yang ,  Mi Sun Yoon

发明人： Byoung Kwan Jeong ,  Chul Woo Yang ,  Mi Sun Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.

摘要翻译： 非易失性存储器件的编程方法包括：输入步骤，用于将程序数据输入到每个页缓冲器的第一锁存器，并将冗余数据输入到每个页缓冲器的第二锁存器;验证结果存储步骤，用于执行程序 使用存储在第一锁存器中的程序数据对所选择的存储器单元进行操作，执行用于程序操作的验证操作，并将验证操作的结果存储在与所选择的存储器单元耦合的每个页缓冲器的第一锁存器中 验证结果改变步骤，用于使用存储在第二锁存器中的冗余数据来改变存储在第一锁存器中的结果;以及验证检查步骤，用于在验证结果改变步骤之后确定存储在第二锁存器中的所有数据是否是程序通过数据 。

公开(公告)号：US08514633B2

公开(公告)日：2013-08-20

申请号：US12982654

申请日：2010-12-30

申请人： Byoung Kwan Jeong

发明人： Byoung Kwan Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483

摘要： A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value.

摘要翻译： 一种用于操作半导体存储器件的方法包括以下步骤：擦除存储器块的存储器单元以将存储器单元设置为第一擦除状态，对存储器块的存储单元的一部分进行编程以将其转换为编程状态， 提高所述存储器块的所选存储单元的阈值电压，并将选择的存储单元从编程状态转换为第二擦除状态，以及在第一擦除状态，编程状态和第二擦除状态下从存储器单元读取数据， 并以相同的值输出从第一和第二擦除状态的存储单元读出的数据。

公开(公告)号：US08374036B2

公开(公告)日：2013-02-12

申请号：US12618973

申请日：2009-11-16

申请人： Byoung Kwan Jeong ,  Chul Woo Yang

发明人： Byoung Kwan Jeong ,  Chul Woo Yang

IPC分类号： G11C16/04

CPC分类号： G11C7/00 ,  G11C16/10 ,  G11C16/16 ,  G11C16/349 ,  G11C16/3495

摘要： A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.

摘要翻译： 一种操作非易失性存储器件的方法包括：读取擦除次数信息，其中，擦除次数信息，当擦除次数被执行时被更新和存储，根据擦除次数信息设置程序启动电压和步进电压，并且基于程序启动电压执行编程操作 阶梯电压。

公开(公告)号：US20100306582A1

公开(公告)日：2010-12-02

申请号：US12779252

申请日：2010-05-13

申请人： Jung Chul Han ,  Byoung Kwan Jeong

发明人： Jung Chul Han ,  Byoung Kwan Jeong

IPC分类号： G06F11/00 ,  G11C29/00

CPC分类号： G06F11/1068 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A method of operating a nonvolatile memory device includes performing a program operation on memory cells included in a selected page, checking whether a verification operation for the programmed memory cells is passed or failed by performing the verification operation, counting a number of error bits for the selected page, if the verification operation is failed, performing an error checking and correction (ECC) algorithm using an error correction circuit, if the counted number of error bits is less than or equal to a number of correctable bits, and storing the counted number of error bits in a specific one of a plurality of memory blocks.

摘要翻译： 一种操作非易失性存储器件的方法包括：对包括在所选择的页面中的存储器单元执行编程操作，通过执行验证操作来检查所编程的存储器单元的验证操作是否通过或失败， 如果验证操作失败，则使用错误校正电路执行错误校验（ECC）算法，如果计数的错误比特数小于或等于可校正比特数，并且存储计数的数 的多个存储块中的特定一个中的错误位。