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6 条记录 (耗时 0.048 秒)

    Phase frequency detector
    5.
    发明申请
    Phase frequency detector 无效

    公开(公告)号：US20060055434A1

    公开(公告)日：2006-03-16

    申请号：US11023379

    申请日：2004-12-29

    申请人： Geum-Young Tak ,  Seok-Bong Hyun ,  Kyung-Hwan Park ,  Tae-Young Kang ,  Seong-Su Park

    发明人： Geum-Young Tak ,  Seok-Bong Hyun ,  Kyung-Hwan Park ,  Tae-Young Kang ,  Seong-Su Park

    IPC分类号： H03K9/06

    CPC分类号： H03L7/0891 ,  H03D13/004

    摘要： Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time and a reset signal, a second stage operated according to the reference clock and an output of the first stage, and an inverter for inverting an output of the second stage; a DOWN signal output unit having: a first stage operated according to an outer clock delayed by a predetermined time and the reset signal, a second stage operated according to the outer clock and an output of the first stage, and an inverter for inverting an output of the second stage; and a logic gate logically combining the output of the second stage of the UP signal output unit and the output of the second stage of the DOWN signal output unit to generate the reset signal, thereby a phase range of the input signal with which an effective control signal can be obtained is wide so that low power consumption and low noise characteristics can be obtained due to fast phase lock, low power consumption of a dynamic logic, and fast signal transmission.

    Phase frequency detector
    6.
    发明授权
    Phase frequency detector 无效
    相频检测器

    公开(公告)号：US07053666B2

    公开(公告)日：2006-05-30

    申请号：US11023379

    申请日：2004-12-29

    申请人： Geum-Young Tak ,  Seok-Bong Hyun ,  Kyung-Hwan Park ,  Tae-Young Kang ,  Seong-Su Park

    发明人： Geum-Young Tak ,  Seok-Bong Hyun ,  Kyung-Hwan Park ,  Tae-Young Kang ,  Seong-Su Park

    IPC分类号： G01R25/00 ,  H03D13/00

    CPC分类号： H03L7/0891 ,  H03D13/004

    摘要： Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time and a reset signal, a second stage operated according to the reference clock and an output of the first stage, and an inverter for inverting an output of the second stage; a DOWN signal output unit having: a first stage operated according to an outer clock delayed by a predetermined time and the reset signal, a second stage operated according to the outer clock and an output of the first stage, and an inverter for inverting an output of the second stage; and a logic gate logically combining the output of the second stage of the UP signal output unit and the output of the second stage of the DOWN signal output unit to generate the reset signal, thereby a phase range of the input signal with which an effective control signal can be obtained is wide so that low power consumption and low noise characteristics can be obtained due to fast phase lock, low power consumption of a dynamic logic, and fast signal transmission.

    摘要翻译： 提供了一种用于锁相环（PLL）或延迟锁定环（DLL）的相位频率检测器，所述相位频率检测器包括：UP信号输出单元，具有根据延迟预定值的参考时钟操作的第一级 时间和复位信号，根据参考时钟操作的第二级和第一级的输出;以及用于反转第二级的输出的反相器; DOWN信号输出单元，具有：根据延迟预定时间的外部时钟和复位信号操作的第一级，根据外部时钟操作的第二级和第一级的输出;以及用于将输出 的第二阶段 逻辑门逻辑地组合UP信号输出单元的第二级的输出和DOWN信号输出单元的第二级的输出，以产生复位信号，从而使输入信号的相位范围成为有效控制 可以获得宽的信号，由于快速锁相，动态逻辑的低功耗和快速信号传输，可以获得低功耗和低噪声特性。