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1.发明授权Dram cell and array to store two-bit data having merged stack capacitor and trench capacitor 失效Dram单元和阵列存储具有合并堆叠电容器和沟槽电容器的两位数据
公开(公告)号：US5920785A
公开(公告)日：1999-07-06
申请号：US18457
申请日：1998-02-04
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/108
摘要： A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.
摘要翻译： 公开了能够存储DRAM单元中存储电荷的两位数字数据的双位DRAM单元。 双位DRAM单元具有双通道晶体管，沟槽电容器和堆叠电容器。 传输晶体管各自具有连接到位线电压发生器的源，以控制双位DRAM单元内的电荷的放置，连接到字线电压发生器的栅极以控制DRAM单元的激活和漏极。 沟槽电容器具有连接到第一通过晶体管的漏极的顶板和连接到第一偏置电压源的底板。 堆叠电容器具有连接到第二通过晶体管的漏极的第一板和连接到第二偏置电压发生器的第二板。 双位DRAM单元将被布置成多个行和列以形成双位DRAM单元的阵列。
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2.发明授权DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor 有权DRAM单元和阵列存储具有合并堆叠电容器和沟槽电容器的两位数据公开(公告)号：US06184548B2
公开(公告)日：2001-02-06
申请号：US09257837
申请日：1999-02-25
IPC分类号： H01L27108
CPC分类号： H01L27/108
摘要： A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.
摘要翻译： 公开了能够存储DRAM单元中存储电荷的两位数字数据的双位DRAM单元。 双位DRAM单元具有双通道晶体管，沟槽电容器和堆叠电容器。 传输晶体管各自具有连接到位线电压发生器的源，以控制双位DRAM单元内的电荷的放置，连接到字线电压发生器的栅极以控制DRAM单元的激活和漏极。 沟槽电容器具有连接到第一通过晶体管的漏极的顶板和连接到第一偏置电压源的底板。 堆叠电容器具有连接到第二通过晶体管的漏极的第一板和连接到第二偏置电压发生器的第二板。 双位DRAM单元将被布置成多个行和列以形成双位DRAM单元的阵列。
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3.发明授权Method of forming shallow trench isolation for integrated circuit applications 失效形成用于集成电路应用的浅沟槽隔离的方法
公开(公告)号：US6080628A
公开(公告)日：2000-06-27
申请号：US79602
申请日：1998-05-15
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76224
摘要： A new and improved method for fabricating planarized isolation trenches, wherein erosion of insulating material at the edges of trenches is surpressed without sacrificing a minimal width of the isolation trench, has been developed. The process fabricates sidewall spacers before etching the isolation trench into the semiconductor substrate. After filling the etched trench with insulating material and plartarization of the insulating material, the sidewall spacers protect the insulating material filling the trench and prevent the formation of "divots" at the edges of the trench. Since the spacers are formed prior to the etching of the trench in the semiconductor substrate, a minimal width of the isolation trench can be maintained and less area is required for the isolation trench.
摘要翻译： 已经开发了用于制造平坦化隔离沟槽的新的和改进的方法，其中在不牺牲隔离沟槽的最小宽度的情况下抑制沟槽边缘处的绝缘材料的侵蚀。 在将隔离沟槽蚀刻到半导体衬底之前，该工艺制造侧壁间隔物。 在用绝缘材料填充蚀刻的沟槽和绝缘材料的一部分之后，侧壁间隔件保护填充沟槽的绝缘材料，并防止在沟槽边缘形成“凸起”。 由于在半导体衬底中的沟槽的蚀刻之前形成间隔物，所以可以保持隔离沟槽的最小宽度并且隔离沟槽需要较少的面积。
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4.发明授权Method to improve yield for capacitors formed using etchback of polysilicon hemispherical grains 失效提高使用多晶硅半球形晶粒回蚀的电容器产量的方法
公开(公告)号：US5874336A
公开(公告)日：1999-02-23
申请号：US880953
申请日：1997-06-23
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84
摘要： A method is described for forming capacitor plates with extended surface area using polysilicon hemispherical grains or HSG polysilicon. The HSG polysilicon is formed on the top surface and sidewalls of first capacitor plates. A vertical anisotropic etching step forms an irregular top surface of the first capacitor plates and an anneal step provides good adhesion between the grains of HSG polysilicon and the sidewalls of the first capacitor plates. A timed etchback of the dielectric between the first capacitor plates insures good electrical insulation between adjacent first capacitor plates.
摘要翻译： 描述了使用多晶硅半球形晶粒或HSG多晶硅形成具有扩展表面积的电容器板的方法。 HSG多晶硅形成在第一电容器板的顶表面和侧壁上。 垂直各向异性蚀刻步骤形成第一电容器板的不规则顶表面，并且退火步骤在HSG多晶硅的晶粒和第一电容器板的侧壁之间提供良好的粘合。 第一电容器板之间的电介质的定时回蚀确保相邻的第一电容器板之间的良好的电绝缘。
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5.发明授权Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices 失效制造用于动态随机存取存储器（DRAM）器件的平面化电容器 - 位位线结构的方法
公开(公告)号：US6010933A
公开(公告)日：2000-01-04
申请号：US118036
申请日：1998-07-17
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A method for making a planarized capacitor-over-bit lines structure on dynamic random access memory devices was achieved. After forming the array of FETs for the memory cells, a first polysilicon layer is deposited and patterned to simultaneously form bit lines and polysilicon landing pads that also form the node contacts for stacked capacitors. A thick first insulating layer is deposited and planarized. Node contact openings are etched in the first insulating layer to the landing pads and a thin second polysilicon layer is deposited which also fills the contact openings. Trenches are etched through the second polysilicon layer and into the first insulating layer around the desired capacitor areas while protecting the remaining DRAM chip area from etching. A thin third polysilicon layer is deposited and etched back to form sidewall spacers and to form capacitor bottom electrodes with increased capacitance. A thin interelectrode dielectric layer is deposited followed by a relatively thin fourth polysilicon layer. A photoresist mask is used to pattern the thin fourth polysilicon to form the capacitor plate electrode and to concurrently etch the thin second polysilicon to the planar first insulating layer providing an array of memory cells that are essentially planar with the peripheral areas of the DRAM chip areas.
摘要翻译： 实现了一种在动态随机存取存储器件上形成平面化的电容器 - 位线结构的方法。 在形成用于存储器单元的FET阵列之后，沉积和图案化第一多晶硅层，以同时形成也形成叠层电容器的节点触点的位线和多晶硅着陆焊盘。 沉积厚的第一绝缘层并平坦化。 节点接触开口在第一绝缘层中蚀刻到着陆焊盘，并且沉积薄的第二多晶硅层，其也填充接触开口。 通过第二多晶硅层蚀刻沟槽并围绕所需的电容器区域进入第一绝缘层，同时保护剩余的DRAM芯片区域免受蚀刻。 沉积薄的第三多晶硅层并回蚀以形成侧壁间隔物并形成具有增加的电容的电容器底部电极。 沉积薄的电极间电介质层，然后沉积相对薄的第四多晶硅层。 使用光致抗蚀剂掩模来对薄的第四多晶硅进行成形以形成电容器板电极，并且同时将薄的第二多晶硅蚀刻到平面的第一绝缘层，从而提供与DRAM芯片区域的外围区域基本上平面的存储器单元的阵列 。
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6.发明授权Method for making self-aligned node contacts to bit lines for capacitor-over-bit-line structures on dynamic random access memory (DRAM) devices 失效用于使自对准节点接触到用于动态随机存取存储器（DRAM）器件上的位线电容结构的位线的方法
公开(公告)号：US5837577A
公开(公告)日：1998-11-17
申请号：US66010
申请日：1998-04-24
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for making memory cells having self-aligned node contacts to bit lines was achieved. After forming the array of FETs for the memory cells, a first insulating layer is deposited and planarized. A single masking step is used to concurrently etch bit lines and node contact openings for crown capacitors. A second polysilicon layer and a silicide layer are deposited to form a polycide layer which is specially patterned to form bit lines with portions of the polycide layer extending over the node contacts. A second insulating layer (e.g., BPSG) is deposited and openings are etched aligned over the node contacts to the polycide. The polycide is selectively etched in the openings to electrically isolate the individual bit lines and concurrently form self-aligned node contacts. A third insulating layer is deposited and etched back to form insulating sidewall liners on the bit lines. A third polysilicon layer is deposited and polished back to form an array of bottom electrodes in the openings for crown capacitors. An interdielectric layer and a fourth polysilicon layer are deposited, and the fourth polysilicon layer is patterned to complete the array of crown capacitors for the DRAM device.
摘要翻译： 实现了一种使具有自对准节点接触到位线的存储单元的方法。 在形成用于存储器单元的FET阵列之后，第一绝缘层被沉积并平坦化。 单个屏蔽步骤用于同时蚀刻冠状电容器的位线和节点接触开口。 沉积第二多晶硅层和硅化物层以形成多晶硅化物层，其被特别图案化以形成位线，其中多晶硅化物层的部分在节点触点上延伸。 沉积第二绝缘层（例如，BPSG），并且在节点触点上蚀刻开口以蚀刻到多晶硅化合物上。 在开口中选择性地蚀刻多晶硅化物以电隔离各个位线并同时形成自对准节点接触。 第三绝缘层被沉积并回蚀刻以在位线上形成绝缘侧壁衬里。 将第三多晶硅层沉积并抛光回形成在用于冠状电容器的开口中的底部电极阵列。 沉积介电层和第四多晶硅层，并且将第四多晶硅层图案化以完成用于DRAM器件的冠状电容器阵列。
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