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    Nonvolatile memory device and methods of forming the same
    5.
    发明授权
    Nonvolatile memory device and methods of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US07618864B2

    公开(公告)日：2009-11-17

    申请号：US11589178

    申请日：2006-10-30

    申请人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

    发明人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7887

    摘要： Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

    摘要翻译： 示例性实施例涉及半导体存储器件及其形成方法。 其他示例实施例涉及非易失性存储器件及其形成方法。 存储器件可以包括分别形成在形成在衬底上的杂质区域之间的沟道区上的存储器单元。 存储单元可各自包括具有隧道绝缘层，形成在存储层上的绝缘层，纳米尺寸电荷存储层以及阻挡绝缘层和侧栅极的存储层。 根据示例实施例，可以实现非易失性存储器件的更大比例的集成，并且存储器件的可靠性可能增加。

    Semiconductor Devices Having a Support Structure for an Active Layer Pattern and Methods of Forming the Same
    6.
    发明申请
    Semiconductor Devices Having a Support Structure for an Active Layer Pattern and Methods of Forming the Same 有权
    具有活性层图案的支撑结构的半导体器件及其形成方法

    公开(公告)号：US20110248376A1

    公开(公告)日：2011-10-13

    申请号：US13166867

    申请日：2011-06-23

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

    IPC分类号： H01L29/06

    CPC分类号： H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

    摘要： Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

    摘要翻译： 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

    Split gate flash memory device having self-aligned control gate and method of manufacturing the same
    7.
    发明授权
    Split gate flash memory device having self-aligned control gate and method of manufacturing the same 有权
    具有自对准控制门的分体式闪存器件及其制造方法

    公开(公告)号：US07652322B2

    公开(公告)日：2010-01-26

    申请号：US12014262

    申请日：2008-01-15

    申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

    发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

    摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

    Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same
    8.
    发明申请
    Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same 有权
    具有部分厚度差的栅极介电层的晶体管及其制造方法

    公开(公告)号：US20060154410A1

    公开(公告)日：2006-07-13

    申请号：US11329623

    申请日：2006-01-11

    申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

    发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

    IPC分类号： H01L21/338 ,  H01L21/425

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

    摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

    摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

    TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME 审中-公开
    具有部分厚度差异的栅介质层的晶体管及其制造方法

    公开(公告)号：US20080283879A1

    公开(公告)日：2008-11-20

    申请号：US12182593

    申请日：2008-07-30

    申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

    发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

    IPC分类号： H01L29/00

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

    摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

    摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

    Nonvolatile memory device and methods of forming the same
    10.
    发明申请
    Nonvolatile memory device and methods of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US20070141796A1

    公开(公告)日：2007-06-21

    申请号：US11589178

    申请日：2006-10-30

    申请人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

    发明人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7887

    摘要： Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

    摘要翻译： 示例性实施例涉及半导体存储器件及其形成方法。 其他示例实施例涉及非易失性存储器件及其形成方法。 存储器件可以包括分别形成在形成在衬底上的杂质区域之间的沟道区上的存储器单元。 存储单元可各自包括具有隧道绝缘层，形成在存储层上的绝缘层，纳米尺寸电荷存储层以及阻挡绝缘层和侧栅极的存储层。 根据示例实施例，可以实现非易失性存储器件的更大比例的集成，并且存储器件的可靠性可能增加。