公开(公告)号：US20120108031A1

公开(公告)日：2012-05-03

申请号：US13346935

申请日：2012-01-10

申请人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/02

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20130221313A1

公开(公告)日：2013-08-29

申请号：US13452544

申请日：2012-04-20

申请人： Ming-Daou LEE ,  ChiaHua HO ,  Cho-Lun HSU ,  Wen-Cheng CHIU

发明人： Ming-Daou LEE ,  ChiaHua HO ,  Cho-Lun HSU ,  Wen-Cheng CHIU

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L45/00 ,  H01L27/1052 ,  H01L27/2472 ,  H01L45/146

摘要： The present invention discloses an ultra high density resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area.

摘要翻译： 本发明公开了一种超高密度电阻式存储器结构及其制造方法。 存储器结构包括多个存储单元。 每个存储单元还包括由上电极制成的两个分离的上子电极，由下电极制造的两个分开的下子电极并且与上子电极相交，以及布置在上子电极和下电极之间的电阻层 子电极。 由此，在两个上部子电极，两个下部子电极和电阻层的交叉点形成四个子存储单元。 从而增加了存储器结构在相同区域中的密度。