公开(公告)号：US20180331281A1

公开(公告)日：2018-11-15

申请号：US16046189

申请日：2018-07-26

申请人： Intel Corporation

发明人： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC分类号： H01L45/00 ,  G11C14/00 ,  G11C11/16 ,  H01L27/24 ,  H01L27/02 ,  G11C13/00 ,  G11C11/00 ,  G11C8/16 ,  G06F12/02

CPC分类号： H01L45/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C13/0007 ,  G11C13/0026 ,  G11C14/0018 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US09954167B2

公开(公告)日：2018-04-24

申请号：US15266181

申请日：2016-09-15

申请人： Toshiba Memory Corporation

发明人： Shosuke Fujii ,  Takayuki Ishikawa

IPC分类号： H01L45/00 ,  H01L27/105 ,  H01L49/00

CPC分类号： H01L45/14 ,  G11C13/0007 ,  H01L27/105 ,  H01L27/2436 ,  H01L45/00 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1253 ,  H01L45/146 ,  H01L49/00

摘要： According to one embodiment, a memory device includes a first layer, a second layer, and a third layer provided between the first layer and the second layer. The first layer includes first interconnections and a first insulating portion. The first interconnections extend in a first direction. The first insulating portion is provided between the first interconnections. The second layer includes a plurality of second interconnections and a second insulating portion. The second interconnections extend in a second direction crossing the first direction. The second insulating portion is provided between the second interconnections. The third layer includes a ferroelectric portion and a paraelectric portion. The ferroelectric portion and the paraelectric portion include hafnium oxide.

公开(公告)号：US09922711B2

公开(公告)日：2018-03-20

申请号：US15499519

申请日：2017-04-27

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C11/00 ,  G11C14/00 ,  G11C13/00 ,  H01L27/108 ,  H01L27/24 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C14/0045 ,  G11C11/21 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4072 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0027 ,  G11C14/0036 ,  G11C14/009 ,  G11C2013/0073 ,  H01L27/10802 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

公开(公告)号：US09911788B2

公开(公告)日：2018-03-06

申请号：US15308923

申请日：2014-05-05

申请人： Hewlett Packard Enterprise Development LP

发明人： Jianhua Yang ,  Ning Ge ,  Zhiyong Li

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2418 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： A selector with an oxide-based layer includes an oxide-based layer that has a first region and a second region. The first region contains a metal oxide in a first oxidation state, and the second region contains the metal oxide in a second oxidation state. The first region also forms a part of each of two opposite faces of the oxide-based layer.

公开(公告)号：US20180025765A1

公开(公告)日：2018-01-25

申请号：US15520932

申请日：2015-10-23

申请人： Sony Corporation

发明人： Takashi Yokoyama ,  Shunsaku Tokito ,  Hiroshi Hasegawa ,  Hajime Yamagishi

IPC分类号： G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC分类号： G11C11/1697 ,  G11C14/0081 ,  H01L27/105 ,  H01L27/11 ,  H01L27/228 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L49/00

摘要： A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

公开(公告)号：US09804491B1

公开(公告)日：2017-10-31

申请号：US15084775

申请日：2016-03-30

申请人： Rudraskandan Ratnadurai ,  Subramanian Krishnan ,  Shekhar Bhansali

发明人： Rudraskandan Ratnadurai ,  Subramanian Krishnan ,  Shekhar Bhansali

IPC分类号： H01L29/40 ,  G03F7/00 ,  H01L49/02 ,  H01L29/861 ,  G03F1/42

CPC分类号： G03F7/0035 ,  G03F1/42 ,  H01L21/283 ,  H01L21/76895 ,  H01L27/24 ,  H01L28/20 ,  H01L28/40 ,  H01L29/408 ,  H01L29/66151 ,  H01L29/861 ,  H01L45/00

摘要： In one embodiment, a mask set for use in fabricating thin film tunneling devices includes a first photomask configured to form bottom electrodes of the devices, the first photomask comprising a first alignment mark including multiple corner markers, and a second photomask configured to form a continuous top layer of the devices, the second photomask comprising a second alignment mark including a corner marker configured to be aligned with one of the corner markers of the first photomask, wherein a degree of overlap between the bottom electrodes and the continuous top layer depends upon the corner marker of the first photomask with which the corner marker of the second photomask aligns.

公开(公告)号：US09773802B2

公开(公告)日：2017-09-26

申请号：US15209371

申请日：2016-07-13

申请人： Samsung Electronics Co., Ltd.

发明人： Xianyu Wenxu ,  Inkyeong Yoo ,  Hojung Kim ,  Seong ho Cho

IPC分类号： H01L29/792 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L21/308 ,  H01L29/08 ,  H01L29/06 ,  G11C11/54 ,  H01L29/68 ,  H01L45/00 ,  H01L29/66 ,  H01L27/105

CPC分类号： H01L27/1157 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/53 ,  G11C2213/79 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66833 ,  H01L29/685 ,  H01L45/00

摘要： Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.

公开(公告)号：US09701115B2

公开(公告)日：2017-07-11

申请号：US15032551

申请日：2013-10-31

申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

发明人： Jianhua Yang ,  Ning Ge ,  Zhiyong Li

IPC分类号： B41J2/14 ,  B41J2/16 ,  B41J2/045

CPC分类号： B41J2/14072 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2/14016 ,  B41J2/14129 ,  B41J2/1601 ,  B41J2/1607 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2202/13 ,  H01L21/02565 ,  H01L27/24 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1675

摘要： Printheads having memories formed thereon are disclosed. An example apparatus includes a printhead body comprising a first metal layer. The example apparatus also include a memory formed on the print-head body. The memory includes the first metal layer as a first electrode, a second metal layer as a second electrode, and a switching oxide layer between the first and second metal layers.

公开(公告)号：US09691912B1

公开(公告)日：2017-06-27

申请号：US14792966

申请日：2015-07-07

申请人： Jing Wang ,  I-Tsang Wu

发明人： Jing Wang ,  I-Tsang Wu

IPC分类号： H01L29/88 ,  H01L29/06

CPC分类号： H01L29/88 ,  H01L29/0665 ,  H01L29/66151 ,  H01L45/00

摘要： In one embodiment, a device includes a substrate having a top surface and cavity that defines generally vertical walls, a thin film of material that has been deposited on the walls of the cavity, and a further material that fills the cavity, wherein a top edge of the thin film is exposed and forms a trace that is flush with the top surface of the substrate and has substrate material on one side and the further material on the other side.

公开(公告)号：US09590015B2

公开(公告)日：2017-03-07

申请号：US14537480

申请日：2014-11-10

申请人： Rutgers, The State University of New Jersey

发明人： Yicheng Lu ,  Yang Zhang ,  Chieh-Jen Ku

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  H01L29/786 ,  H01L29/24 ,  H01L29/872

CPC分类号： H01L27/2481 ,  G11C2213/53 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/872 ,  H01L45/00 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

摘要： A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.

摘要翻译： 公开了一种垂直集成的可重构和可编程二极管/存储器电阻（1D1R）和衬底上的薄膜晶体管/存储电阻（1T1R）结构。