公开(公告)号：US06279098B1

公开(公告)日：2001-08-21

申请号：US08767455

申请日：1996-12-16

申请人： Mitchell A. Bauman ,  Lewis A. Boone ,  Donald E. Schroeder

发明人： Mitchell A. Bauman ,  Lewis A. Boone ,  Donald E. Schroeder

IPC分类号： G06F1500

CPC分类号： G06F9/5077

摘要： A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/O ASIC pin, and a single PC board trace. In addition to reducing the required number of I/O ASIC pins and PC board traces, the present invention may increase the overall reliability of the partitioning mechanism.

摘要翻译： 一种用于在系统分区之间以及在系统分区与相应的数据处理资源之间串行发送分区信息的方法和装置。 串行传输可以允许使用单个I / O ASIC引脚和单个PC板跟踪传输分区信息。 除了减少所需数量的I / O ASIC引脚和PC板迹线之外，本发明可以增加分区机构的整体可靠性。

公开(公告)号：US07343515B1

公开(公告)日：2008-03-11

申请号：US10954842

申请日：2004-09-30

申请人： R. Lee Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson

发明人： R. Lee Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0712 ,  G06F11/0724

摘要： A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.

摘要翻译： 公开了一种用于在支持多个处理分区的数据处理系统中执行错误恢复的系统和方法。 一个或多个处理器和I / O模块以及主存储器的地址空间的一部分被分配给每个分区。 在这种类型的配置中，由多个分区的单元生成的请求由主存储器的相同队列和状态逻辑处理。 当在一个处理分区内发生故障时，一个或多个单元被识别为直接受故障影响。 受影响单位的所有请求和响应以及这些请求和响应的任何逻辑残差都以共享内存队列和状态逻辑的方式被删除，从而允许其他分区继续发出请求和响应 记忆以不涉及恢复操作的正常方式。

公开(公告)号：US07167955B1

公开(公告)日：2007-01-23

申请号：US10745372

申请日：2003-12-23

申请人： Justin S. Neils ,  John S. Jensen ,  Mitchell A. Bauman ,  Eugene A. Rodi ,  Bart E. Reigstad

发明人： Justin S. Neils ,  John S. Jensen ,  Mitchell A. Bauman ,  Eugene A. Rodi ,  Bart E. Reigstad

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F11/1008 ,  G06F2212/1032

摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.

摘要翻译： 用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。 在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块 响应于存储器请求确定所请求的数据条目的下一目录状态。 为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。 另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。 选择器的输出可能会写入目录存储。

公开(公告)号：US06594785B1

公开(公告)日：2003-07-15

申请号：US09561270

申请日：2000-04-28

申请人： Roger L. Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson ,  James L. DePenning ,  Michael L. Haupt ,  Donald Kalvestrand ,  Daniel S. Tokoly ,  Frederick G. Fellenser ,  Maria A. Liedman

发明人： Roger L. Gilbertson ,  Mitchell A. Bauman ,  Penny L. Svenkeson ,  James L. DePenning ,  Michael L. Haupt ,  Donald Kalvestrand ,  Daniel S. Tokoly ,  Frederick G. Fellenser ,  Maria A. Liedman

IPC分类号： H02H305

CPC分类号： G06F11/0772 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/0793

摘要： Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.

摘要翻译： 当多处理器计算机系统的一部分变得有故障时，将特定存储器位置中毒作为过程导致即使在共享存储器区域中也能够分离由单个故障单元拥有的特定数据的能力。 也可以由非故障单元进行连续处理。 支持处理器处理非直接问题，并允许重置以前由故障单元拥有的存储器位置。

公开(公告)号：US06587931B1

公开(公告)日：2003-07-01

申请号：US09001598

申请日：1997-12-31

申请人： Mitchell A. Bauman ,  Eugene A. Rodi ,  Douglas E. Morrissey

发明人： Mitchell A. Bauman ,  Eugene A. Rodi ,  Douglas E. Morrissey

IPC分类号： G06F1208

CPC分类号： G06F12/0817 ,  G06F12/0886 ,  G06F2212/621

摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.

摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

公开(公告)号：US06477620B1

公开(公告)日：2002-11-05

申请号：US09467190

申请日：1999-12-20

申请人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Donald R. Kalvestrand ,  Joseph S. Schibinger ,  Daniel S. Tokoly

发明人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Donald R. Kalvestrand ,  Joseph S. Schibinger ,  Daniel S. Tokoly

IPC分类号： G06F1208

CPC分类号： G06F12/0813 ,  G06F12/0811

摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.

摘要翻译： 公开了一种用于分级，多级存储器的数据旁路系统。 旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。 优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。 为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。 可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。

公开(公告)号：US06356991B1

公开(公告)日：2002-03-12

申请号：US09001390

申请日：1997-12-31

申请人： Mitchell A. Bauman ,  Roger L. Gilbertson

发明人： Mitchell A. Bauman ,  Roger L. Gilbertson

IPC分类号： G06F1206

CPC分类号： G06F12/0607 ,  G06F12/0292

摘要： A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving. Each GRA may be re-programmed dynamically to accommodate changing memory conditions as may occur, for example, when a range of memory is logically removed from a system because of errors. Furthermore, GRA reprogramming may occur while memory operations continue within other non-associated address ranges. Additionally, address interleaving may be selected for certain ones of the address ranges, whereas a non-interleaving scheme may be selected for other address ranges.

摘要翻译： 提供了一种用于模块化主存储器的可编程地址转换系统。 该系统使用一个或多个通用寄存器阵列（GRA）实现，其中每个GRA对系统内的预定地址范围进行逻辑到物理地址转换。 使用逻辑地址的预定比特来寻址与逻辑地址范围相关联的GRA。 然后将从GRA读取的数据位代替逻辑地址的预定位以形成物理地址。 以这种方式，物理存储器的不连续可寻址组可以被映射到可选择的相邻地址范围。 通过在GRA地址内包含用于寻址连续逻辑地址的N个逻辑地址位，提供地址转换机制，其可被编程为在2路和2N路地址交错之间执行。 可以动态地重新编程每个GRA以适应可能发生的变化的存储器条件，例如当由于错误而从系统逻辑地移除存储器的范围时。 此外，当存储器操作在其他非关联地址范围内继续时，可能会发生GRA重新编程。 另外，可以针对某些地址范围来选择地址交织，而对于其他地址范围可以选择非交织方案。

公开(公告)号：US5960455A

公开(公告)日：1999-09-28

申请号：US777038

申请日：1996-12-30

申请人： Mitchell A. Bauman

发明人： Mitchell A. Bauman

IPC分类号： G06F12/08

CPC分类号： G06F12/0811

摘要： Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.

摘要翻译： 一种计算机系统的方法和装置，用于在对称的多处理环境中有效地操作多个指令处理器和输入/输出子系统。 计算机系统使用具有高性能互连方案的新的存储控制器，其增加了附加的公共存储控制器模块来扩展系统性能。 互连方案具有总线连接系统的成本优势，同时实现了交叉连接系统的性能特征。

公开(公告)号：US20130132061A1

公开(公告)日：2013-05-23

申请号：US13299458

申请日：2011-11-18

申请人： Michael J. Rieschl ,  Mitchell A. Bauman ,  Feng-Jung Kao ,  Edward Lusienski ,  James R. McBreen ,  James F. Merten ,  Thomas L. Nowatzki ,  David W. Schroth ,  Scott L. Titus ,  Judge Yohn ,  Nathan Zimmer

发明人： Michael J. Rieschl ,  Mitchell A. Bauman ,  Feng-Jung Kao ,  Edward Lusienski ,  James R. McBreen ,  James F. Merten ,  Thomas L. Nowatzki ,  David W. Schroth ,  Scott L. Titus ,  Judge Yohn ,  Nathan Zimmer

IPC分类号： G06F9/455

CPC分类号： G06F9/45554 ,  G06F2009/45583

摘要： A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit. The computing system includes a linker configured to manage association of at least one of the one or more translated memory banks to the interface layer for native execution by the programmable circuit in place of a corresponding bank of non-native instructions.

摘要翻译： 一种用于执行软件程序的计算系统和方法以及用于仿真计算环境的指令的翻译。 计算系统包括能够执行第一指令集架构的本机指令并且不能执行第二指令集架构的非本地指令的可编程电路。 仿真器在接口层内运行，并且转换托管在仿真操作系统中的非本机应用程序以供执行。 计算系统包括至少部分由仿真的操作系统定义的翻译的存储器组，并且能够在可编程电路上进行本地执行，其中仿真操作系统不能在可编程电路上执行。 计算系统包括链接器，其被配置为管理一个或多个翻译的存储器组中的至少一个与接口层的关联，用于由可编程电路代替相应的非本机指令组进行本地执行。

公开(公告)号：US07213109B1

公开(公告)日：2007-05-01

申请号：US10304919

申请日：2002-11-26

申请人： Mitchell A. Bauman ,  Joseph S. Schibinger

发明人： Mitchell A. Bauman ,  Joseph S. Schibinger

IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F3/00 ,  G06F13/18

CPC分类号： G06F12/0817 ,  G06F2212/507

摘要： A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.

摘要翻译： 提供了一种用于管理存储器数据的系统和方法。 存储在主存储器内的数据可以由可能包括一个或多个高速缓存存储器的多个请求者请求。 当主存储器向请求者提供数据时，将以基于请求者最近使用数据的方式提供数据。 例如，如果为数据建立了只读使用模式，则数据将以共享状态返回给请求者。 如果必须更新在共享状态下提供的数据，以便需要请求者返回到主存储器以获得读/写权限，则主存储器此后将以允许写操作完成的独占状态提供数据。 这将继续，直到再次建立只读使用模式。