公开(公告)号：US07528028B2

公开(公告)日：2009-05-05

申请号：US11199011

申请日：2005-08-08

申请人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/7624 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

摘要翻译： 一种用于形成半导体结构的方法包括：提供衬底，在衬底上形成第一器件区域，形成覆盖第一器件区域的应力层，以及对第一器件区域中的应力层进行超退火，优选通过将衬底暴露于 高能量辐射源，使得应力层在超短时间内进行超退火。 优选地，该方法还包括在第一器件区域被超退火时掩蔽衬底上的第二器件区域。 或者，在第一区域中的应力层退火之后，第二器件区域中的应力层被超退火。 使用该方法形成的半导体结构在第一和第二器件区域中具有不同的应变。

公开(公告)号：US20060286758A1

公开(公告)日：2006-12-21

申请号：US11199011

申请日：2005-08-08

申请人： Mong Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Mong Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/7624 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

公开(公告)号：US07741699B2

公开(公告)日：2010-06-22

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

公开(公告)号：US20060284249A1

公开(公告)日：2006-12-21

申请号：US11157515

申请日：2005-06-21

申请人： Chien-Hao Chen ,  Chun-Feng Nieh ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Chun-Feng Nieh ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A pMOS transistor having reduced diffusion from source/drain regions and a method of forming the same are provided. The pMOS transistor includes a source/drain region doped with a p-type impurity and a diffusion-retarding material in a semiconductor substrate. The pMOS transistor further includes a gate dielectric over a channel region in the semiconductor substrate, a gate electrode over the gate dielectric, and a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode. The diffusion-retarding material preferably includes carbon, fluorine, nitrogen, and combinations thereof.

摘要翻译： 提供了具有从源极/漏极区域的扩散减小的pMOS晶体管及其形成方法。 pMOS晶体管包括掺杂有p型杂质的源极/漏极区域和在半导体衬底中的扩散阻滞材料。 pMOS晶体管还包括在半导体衬底中的沟道区域上的栅极电介质，栅极电介质上的栅极电极以及基本上与栅电极的边缘对齐的轻掺杂源极/漏极（LDD）区域。 扩散阻滞材料优选包括碳，氟，氮及其组合。

公开(公告)号：US07482211B2

公开(公告)日：2009-01-27

申请号：US11523274

申请日：2006-09-19

申请人： Chun-Feng Nieh ,  Chien-Hao Chen ,  Keh-Chiang Ku ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chun-Feng Nieh ,  Chien-Hao Chen ,  Keh-Chiang Ku ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在与栅电极的边缘相邻的半导体衬底中形成应力器，并在形成步骤之后注入杂质 压力源。 杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

公开(公告)号：US20070010073A1

公开(公告)日：2007-01-11

申请号：US11175563

申请日：2005-07-06

申请人： Chien-Hao Chen ,  Chun-Feng Nieh ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Mong Liang

发明人： Chien-Hao Chen ,  Chun-Feng Nieh ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Mong Liang

IPC分类号： H01L21/20 ,  H01L21/4763

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.

摘要翻译： 一种形成半导体器件的方法，包括提供包括第一器件区域的衬底，在第一器件区域中注入源极/漏极区域，在源极/漏极区域上形成应变封盖层，超退火并使源极/漏极区域结晶 并且提供基本上所有的应变封盖层的去除。 该方法还包括在超退火之前对源极/漏极区进行非晶化。 应变封盖层可以进一步形成在非晶化的栅电极上，并且栅电极被超退火。 在去除应变封盖层后产生并保存菌株。

公开(公告)号：US07494857B2

公开(公告)日：2009-02-24

申请号：US11648371

申请日：2006-12-29

申请人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

发明人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

IPC分类号： H01L21/336 ,  H01L21/461

CPC分类号： H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成与所述栅极电介质和所述栅电极相邻的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

公开(公告)号：US20070298565A1

公开(公告)日：2007-12-27

申请号：US11523274

申请日：2006-09-19

申请人： Chun-Feng Nieh ,  Chien-Hao Chen ,  Keh-Chiang Ku ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chun-Feng Nieh ,  Chien-Hao Chen ,  Keh-Chiang Ku ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L29/7848 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在与栅电极的边缘相邻的半导体衬底中形成应力器，并在形成步骤之后注入杂质 压力源。 杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

公开(公告)号：US20080160709A1

公开(公告)日：2008-07-03

申请号：US11648371

申请日：2006-12-29

申请人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

发明人： Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ting Wang ,  Hsun Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成邻近所述栅极电介质和所述栅电极的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

公开(公告)号：US20070284615A1

公开(公告)日：2007-12-13

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/739

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。