公开(公告)号：US5885865A

公开(公告)日：1999-03-23

申请号：US851689

申请日：1997-05-06

申请人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

发明人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

IPC分类号： E04G23/02 ,  E04B1/64 ,  H01L21/8242

CPC分类号： E04B1/648

摘要： The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

摘要翻译： 本发明公开了一种制备低地埋式电容器的方法，包括以下步骤：首先沉积氧化物层，然后通过干蚀刻法和大型接触孔通过湿法蚀刻法形成小预接触孔，同时使用氮化硅 预先沉积在字线和位线上的帽和侧壁间隔作为蚀刻停止层。 可以在半导体器件中制造具有显着改善的形貌的埋电容器。

公开(公告)号：US5811331A

公开(公告)日：1998-09-22

申请号：US719236

申请日：1996-09-24

申请人： Tse-Liang Ying ,  Mong-Song Liang

发明人： Tse-Liang Ying ,  Mong-Song Liang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention provides a method of manufacturing a cylindrical capacitor which begins by forming an insulating layer and a passivation layer composed of silicon nitride is over a substrate. A plug contact opening is formed through the passivation layer and the insulating layer. The insulating layer in the plug contact opening is selectively wet etched. The wet etching forms an overhanging portion of the passivation layer. A bottom plug is formed in the contact opening. A first dielectric layer having a cylindrical electrode opening is formed over passivation layer and the plug is exposed. A second polysilicon layer is formed over the first dielectric layer and in the cylindrical openings. A second dielectric layer is formed over the second polysilicon layer and in the cylindrical electrode opening. The second dielectric layer and the second polysilicon layer are planarized. The remaining second polysilicon layer in the cylindrical opening forms a cylindrical capacitor electrode over the bottom electrode plug. The first dielectric layer and the second dielectric layer are etched away. The overhang portion 21 of the passivation layer 20 and the bottom polysilicon plug 32 prevent the etch from etching voids in the underlying insulating layer 14 when the cylindrical electrode 50 is misaligned relative to the plug.

摘要翻译： 本发明提供一种通过形成绝缘层开始的圆柱形电容器的制造方法，并且由氮化硅构成的钝化层在衬底上。 通过钝化层和绝缘层形成插塞接触开口。 插头接触开口中的绝缘层被选择性地湿蚀刻。 湿蚀刻形成钝化层的突出部分。 底塞形成在接触开口中。 在钝化层上形成具有圆柱形电极开口的第一电介质层，并且暴露插头。 第二多晶硅层形成在第一介电层上和圆柱形开口中。 第二电介质层形成在第二多晶硅层上和圆柱形电极开口中。 第二电介质层和第二多晶硅层被平坦化。 圆柱形开口中剩余的第二多晶硅层在底部电极插头上形成圆柱形电容器电极。 第一介电层和第二介电层被蚀刻掉。 当圆柱形电极50相对于插头不对准时，钝化层20的突出部分21和底部多晶硅插塞32防止蚀刻蚀刻下面的绝缘层14中的空隙。

公开(公告)号：US6037222A

公开(公告)日：2000-03-14

申请号：US83271

申请日：1998-05-22

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L27/1052 ,  H01L27/10873

摘要： A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises:(a) forming a first gate oxide layer 20, a first polysilicon layer 24, and a first gate cap layer 28 over said logic area 12;(b) forming memory gate structures 34 36 38 40 42A in memory area 14,(c) forming memory LDD regions 50 adjacent to said memory gate structures 24 26 28 40 in said memory area 14;(d) patterning said first gate oxide layer 20, said first polysilicon layer 24 and said first gate cap layer 28 over said logic area forming logic gate structures 20 24A & 20 24B;(e) forming spacers 66;(f) forming logic Source/drain regions 62;(g) using a salicide process to form self-aligned silicide logic S/D contacts 72 to said Source/drain regions 62, and to form self-aligned silicide logic gate contacts 74 to said logic gate structures 20 24B & 20 24A; and(h) forming self aligned polycide contacts 80 to said memory source/drain regions 50.

摘要翻译： 一种制造具有嵌入式逻辑的存储器件的方法。 存储器和逻辑FETs具有两个不同的两个栅极氧化层20 34的厚度。 该方法集成了（1）自杀式接触过程72 74（逻辑器件）和双栅极（N + / P +）逻辑门24A 24B技术与（2）存储器件Polycide与自对准接触80技术。 该方法包括：（a）在所述逻辑区域12上形成第一栅极氧化物层20，第一多晶硅层24和第一栅极覆盖层28; （b）在存储器区域14中形成存储器栅极结构34 36 38 40 42A，（c）在所述存储区域14中形成与所述存储器栅极结构24 26 28 40相邻的存储器LDD区域50; （d）在所述逻辑区域上形成所述第一栅极氧化物层20，所述第一多晶硅层24和所述第一栅极覆盖层28，形成逻辑门结构20A，24A和20BB; （e）形成间隔件66; （f）形成逻辑源极/漏极区域62; （g）使用自对准硅化物工艺将自对准硅化物逻辑S / D触点72形成到所述源极/漏极区62，并且形成到所述逻辑门结构20 24B和20 24A的自对准硅化物逻辑门触点74; 和（h）将自对准的多晶硅触点80形成到所述存储器源极/漏极区50。

公开(公告)号：US06207492B1

公开(公告)日：2001-03-27

申请号：US09587466

申请日：2000-06-05

申请人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Kevin Chiang

发明人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Kevin Chiang

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873

摘要： A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.

摘要翻译： 已经开发了用于在栅极结构上以及重掺杂的源极/漏极区域上形成具有硅化物形状的逻辑器件的过程，同时仅在栅极结构上形成具有硅化物形状的嵌入式DRAM器件。 该工艺在嵌入式DRAM器件区域中具有形成在栅极结构之间的空间中的氧化硅阻挡形状。 使用高密度等离子体沉积方法形成氧化硅阻挡形状，该方法在嵌入式DRAM器件区域中的栅极结构之间的狭窄空间中沉积厚的氧化硅层，并且在栅极结构中的较宽空间中沉积薄的氧化硅层 逻辑器件区域，并在所有栅极结构的顶表面上。 然后采用全面的干蚀刻方法从所有栅极结构的顶表面以及逻辑器件区域中的栅极结构之间的空间中移除薄氧化硅层，同时在栅极之间形成期望的氧化硅阻挡形状 结构，因此允许仅在栅极结构的顶表面上以及在逻辑器件区域中的重掺杂的源/漏区上形成随后的自对准硅化物形状。

公开(公告)号：US06433665B1

公开(公告)日：2002-08-13

申请号：US09839702

申请日：2001-04-23

申请人： Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

发明人： Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

IPC分类号： H01F500

摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

公开(公告)号：US06278352B1

公开(公告)日：2001-08-21

申请号：US09359892

申请日：1999-07-26

申请人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

发明人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC分类号： H01F500

CPC分类号： H01F5/003

摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

摘要翻译： 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US5753547A

公开(公告)日：1998-05-19

申请号：US789238

申请日：1997-01-28

申请人： Tse-Liang Ying

发明人： Tse-Liang Ying

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention provides a method of manufacturing a stacked cylindrical capacitor having a smooth top cylindrical surface and uniform height. A first insulating layer 20 is formed over the substrate 10. A barrier layer 22 having an opening 23 is formed over a first insulating layer 20 on a substrate. A second insulating layer 24 composed of silicon oxide is formed on the barrier layer 22. The second insulating layer 24 and the first insulating layer 20 are patterned forming a first cylindrical opening 26 exposing the active region of the substrate 10 and forming a second cylindrical opening 30 in the second insulating layer 24 that exposes portions of the barrier layer 22. A conformal polysilicon layer 34 is formed over the resultant surface and the walls of the cylindrical openings 26 30. A planarizing layer 36 is formed over the resulting surface and then etched back forming a planarizing plug 36A that partially fills the second cylindrical opening 30A. A third insulation layer 40 is formed over resultant surface. The third insulating layer 40 and the polysilicon layer 34 are isotropically etched back forming a cylindrical bottom electrode 44 with a smooth top surface 44A. The smooth top electrode surface 44A increases the breakdown voltage to the capacitor.

摘要翻译： 本发明提供一种制造具有平滑顶部圆柱形表面和均匀高度的层叠圆柱形电容器的方法。 第一绝缘层20形成在衬底10上。具有开口23的阻挡层22形成在衬底上的第一绝缘层20上。 在阻挡层22上形成由氧化硅构成的第二绝缘层24.对第二绝缘层24和第一绝缘层20进行图案化，形成露出基板10的有源区的第一圆柱形开口26，并形成第二圆柱形开口 在第二绝缘层24中暴露出阻挡层22的一部分。在合成的表面和圆柱形开口26,30的壁上形成共形多晶硅层34.平坦化层36形成在所得表面上，然后蚀刻 后部形成部分填充第二圆柱形开口30A的平坦化塞子36A。 在合成表面上形成第三绝缘层40。 第三绝缘层40和多晶硅层34被各向同性地回蚀，形成具有光滑顶表面44A的圆柱形底电极44。 光滑的顶部电极表面44A增加了对电容器的击穿电压。

公开(公告)号：US06373369B2

公开(公告)日：2002-04-16

申请号：US09839927

申请日：2001-04-23

申请人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

发明人： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC分类号： H01F500

CPC分类号： H01F5/003

摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

摘要翻译： 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US06287939B1

公开(公告)日：2001-09-11

申请号：US09216789

申请日：1998-12-21

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76895

摘要： The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.

摘要翻译： 本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。 本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。 该过程开始于在半导体衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成氮化物层。 图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。 接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。 填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。 将N 2离子注入填充氧化物区域。 进行退火以形成掩埋的氮氧化物层。 掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。 去除氮化物层。 然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

公开(公告)号：US06214715B1

公开(公告)日：2001-04-10

申请号：US09349841

申请日：1999-07-08

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC分类号： H01L2144

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  H01L28/92

摘要： This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a device layer, a first inter poly oxide layer (IPO-1), and a conductive structure (such as a bit line) thereover, and having a contact area on the device layer adjacent to the conductive structure. The semiconductor structure can further include an optional etch stop layer overlying the first inter poly oxide layer. The conductive structure comprises at least one conductive layer with a hard mask thereover. A first spacer layer is formed over the hard mask and the IPO-1 layer and anisotropically etched to form first sidewall spacers on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask such that the profile of the first sidewall spacers are not concave at any point. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer is formed over the second sidewall spacers, the hard mask, and the IPO-1 layer, whereby the second inter poly oxide layer is free from key holes. A contact opening is formed in the second inter poly oxide layer and the first inter poly oxide layer over the contact area. A contact plug is formed in the contact openings.

摘要翻译： 本发明提供一种用于使用两步侧壁间隔物沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有器件层，第一多晶硅氧化物层（IPO-1）和导电结构（例如位线）的半导体结构，并且在与其相邻的器件层上具有接触区域 导电结构。 半导体结构还可以包括覆盖在第一多晶硅氧化物层上的任选的蚀刻停止层。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和IPO-1层上形成第一间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成直到硬掩模的底部以上的水平并且低于 硬掩模，使得第一侧壁隔片的轮廓在任何点都不是凹的。 第二间隔层形成在第一侧壁间隔物上并且各向异性蚀刻以形成第二侧壁间隔物，其具有在任何点处不凹的轮廓。 在第二侧壁间隔物，硬掩模和IPO-1层上形成第二多晶硅氧化物层，由此第二多晶氧化物层没有键孔。 在接触区域上的第二多晶氧化物层和第一多晶氧化物层中形成接触开口。 在接触开口中形成接触塞。