公开(公告)号：US5885865A

公开(公告)日：1999-03-23

申请号：US851689

申请日：1997-05-06

申请人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

发明人： Mong-Song Liang ,  Julie Huang ,  Tse-Liang Ying ,  Chen-Jong Wang

IPC分类号： E04G23/02 ,  E04B1/64 ,  H01L21/8242

CPC分类号： E04B1/648

摘要： The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

摘要翻译： 本发明公开了一种制备低地埋式电容器的方法，包括以下步骤：首先沉积氧化物层，然后通过干蚀刻法和大型接触孔通过湿法蚀刻法形成小预接触孔，同时使用氮化硅 预先沉积在字线和位线上的帽和侧壁间隔作为蚀刻停止层。 可以在半导体器件中制造具有显着改善的形貌的埋电容器。

公开(公告)号：US5668035A

公开(公告)日：1997-09-16

申请号：US661259

申请日：1996-06-10

申请人： Chung Hsin Fang ,  Julie Huang ,  Chen-Jong Wang ,  Mong-Song Liang

发明人： Chung Hsin Fang ,  Julie Huang ,  Chen-Jong Wang ,  Mong-Song Liang

IPC分类号： H01L27/105 ,  H01L21/70

CPC分类号： H01L27/105

摘要： A method for fabricating a dual-gate oxide for memory with embedded logic has been achieved. The method is described for forming a thin gate oxide for the peripheral circuits on a DRAM device, while providing a thicker oxide for the memory cells having a boosted word line architecture. The method avoids applying photoresist directly to the gate oxide, and thereby prevents contamination. A first gate oxide is formed on the device areas on the substrate. A first polysilicon layer is deposited and patterned leaving portions over the memory cell areas. The first gate oxide is removed over the peripheral device areas, and is replaced by a thinner second gate oxide. A second polysilicon layer is deposited and patterned to remain over the peripheral device areas. The first and second polysilicon layers, having essentially equal thicknesses, are coated with an insulating layer. The FET gate electrodes for both the peripheral and memory cell areas are simultaneously patterned from the first and second polysilicon layers to complete the DRAM structure up to and including the gate electrodes.

摘要翻译： 已经实现了用于具有嵌入式逻辑的用于存储器的双栅极氧化物的方法。 描述了用于在DRAM器件上形成用于外围电路的薄栅极氧化物的方法，同时为具有升压的字线架构的存储器单元提供较厚的氧化物。 该方法避免了将光致抗蚀剂直接施加到栅极氧化物，从而防止污染。 第一栅极氧化物形成在衬底上的器件区域上。 沉积和图案化的第一多晶硅层将部分留在存储器单元区域上。 第一栅极氧化物在外围器件区域上被去除，并被较薄的第二栅极氧化物代替。 第二多晶硅层被沉积并图案化以保留在外围设备区域上。 具有基本相同厚度的第一和第二多晶硅层被涂覆有绝缘层。 用于外围和存储单元区域的FET栅电极从第一和第二多晶硅层同时构图，以完成直到并包括栅电极的DRAM结构。

公开(公告)号：US5723374A

公开(公告)日：1998-03-03

申请号：US775049

申请日：1996-12-27

申请人： Julie Huang ,  Mong-Song Liang

发明人： Julie Huang ,  Mong-Song Liang

IPC分类号： H01L21/8242 ,  H01L23/532

CPC分类号： H01L27/10844 ,  H01L23/53223 ,  H01L2924/0002

摘要： A new method of avoiding the formation of a polysilicon stringer along the slope of the bit line contact hole edge is described. A gate electrode and associated source/drain regions are formed in and on the surface of a semiconductor substrate wherein the bit line contact is to be formed adjacent to the gate electrode. First spacers are formed on the sidewalls of the gate electrode. A first insulating layer over the gate electrode adjacent to the bit line contact has a first slope. Second spacers on the sidewalls of the first insulating layer adjacent to the bit line contact have a second slope less than the first slope. A second polysilicon layer is deposited overlying the gate electrode and patterned. A first dielectric layer and a third polysilicon layer is deposited overlying the second polysilicon layer. The third polysilicon layer is etched away where the bit line contact is to be formed. The gentler slope of the second spacers allows the third polysilicon layer to be etched away without leaving stringers. A bit line contact opening is etched through a second dielectric layer to the underlying semiconductor substrate wherein the bit line contact opening is separated from the third polysilicon layer by a thickness of the second dielectric layer. A fourth polysilicon layer is deposited within the contact opening to form the bit line contact.

摘要翻译： 描述了避免沿着位线接触孔边缘的斜面形成多晶硅桁条的新方法。 在半导体衬底的表面上和表面上形成栅电极和相关的源极/漏极区，其中位线接触将被形成为与栅电极相邻。 在栅电极的侧壁上形成第一间隔物。 与位线接触件相邻的栅电极上的第一绝缘层具有第一斜率。 与位线接触相邻的第一绝缘层的侧壁上的第二间隔物具有小于第一斜率的第二斜率。 第二多晶硅层沉积在栅电极上并被图案化。 覆盖在第二多晶硅层上的第一介电层和第三多晶硅层被沉积。 在要形成位线接触的位置蚀刻掉第三多晶硅层。 第二间隔物的温和倾斜允许第三多晶硅层被蚀刻掉而不留下桁条。 位线接触开口通过第二电介质层蚀刻到下面的半导体衬底，其中位线接触开口与第三多晶硅层分离第二电介质层的厚度。 在接触开口内沉积第四多晶硅层以形成位线接触。

公开(公告)号：US5846860A

公开(公告)日：1998-12-08

申请号：US668801

申请日：1996-06-24

申请人： Chun-Yi Shih ,  Julie Huang ,  Mong-Song Liang

发明人： Chun-Yi Shih ,  Julie Huang ,  Mong-Song Liang

IPC分类号： H01L21/285 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/28537 ,  Y10S148/02

摘要： A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening. The first polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and wherein a portion of a TEOS spacer overlying the buried contact junction is exposed and wherein a portion of the first polysilicon layer other than that of the contact remains as residue. The first polysilicon layer residue is etched away wherein the exposed TEOS spacer protects the buried contact junction within the semiconductor substrate from the etching completing the formation of a buried contact in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 字线设置在半导体衬底的表面上。 第一绝缘层沉积在字线上方。 第一绝缘层被蚀刻掉，其中它不被掩埋的接触掩模覆盖以提供到半导体衬底的开口。 一层四乙氧基硅烷（TEOS）氧化硅沉积在第一绝缘层上方，并在该开口内的半导体衬底上。 TEOS层被各向异性地蚀刻以将间隔物留在字线和第一绝缘层的侧壁上。 第一层多晶硅沉积在第一绝缘层上并且在开口内。 第一多晶硅层掺杂掺杂剂，掺杂剂被驱动以在开口下的半导体衬底内形成掩埋接触结。 第一多晶硅层被图案化以形成覆盖掩埋接触结的多晶硅接触，其中用于图案化的掩模未对准，并且其中覆盖掩埋接触结的TEOS间隔物的一部分被暴露，并且其中第一多晶硅层的一部分其他 比接触物残留物残留。 蚀刻掉第一多晶硅层残留物，其中暴露的TEOS间隔物保护半导体衬底内的掩埋接触结合层免于在集成电路的制造中完成掩埋接触的形成。

公开(公告)号：US5783462A

公开(公告)日：1998-07-21

申请号：US787195

申请日：1997-01-22

申请人： Julie Huang

发明人： Julie Huang

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L21/66 ,  H01L21/8242

CPC分类号： H01L27/10808 ,  H01L27/105

摘要： A structure for forming an ohmic contact to the drain of a MOSFET in a stacked capacitor DRAM cell is described. The contact is formed by making an opening in the upper cell plate of the cells capacitor and contacting the storage plate through this opening with a conductive plug, preferably a tungsten plug. The plug is formed concurrent with the conventional contact and first metal wiring processing of the DRAM. The contact is used in DRAM test arrays for characterizing the quality of MOSFET gate insulator as well as the performance characteristics of the MOSFET itself. Connection to the conductive plug is made with first metal wiring. The test structures can be built at any position within the array and since they are located above the polysilicon bitline/wordline structure, the metal connection lines for the contacts do not interfere with the structure of the test array itself other than the sacrifice of the test cell from the array. Multiple devices may be designated from anywhere in the array, and probe contacts may be conveniently located on the chip.

摘要翻译： 描述了用于在层叠电容器DRAM单元中形成与MOSFET的漏极的欧姆接触的结构。 通过在电池电容器的上电池板中形成开口形成接触，并通过该开口与存储板与导电插塞（优选为钨插塞）接触。 插头与DRAM的常规触点和第一金属布线处理同时形成。 该触点用于DRAM测试阵列，用于表征MOSFET栅极绝缘体的质量以及MOSFET本身的性能特性。 与导电插头的连接由第一金属布线制成。 测试结构可以建立在阵列内的任何位置，并且由于它们位于多晶硅位线/字线结构之上，所以触点的金属连接线不会干扰测试阵列本身的结构，而不是测试的牺牲 单元格从数组。 可以从阵列中的任何地方指定多个器件，并且探针触点可以方便地位于芯片上。

公开(公告)号：US5914512A

公开(公告)日：1999-06-22

申请号：US83253

申请日：1998-05-20

申请人： Julie Huang

发明人： Julie Huang

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10808 ,  H01L27/105

摘要： A structure for forming an ohmic contact to the drain of a MOSFET in a stacked capacitor DRAM cell is described. The contact is formed by making an opening in the upper cell plate of the cells capacitor and contacting the storage plate through this opening with a conductive plug, preferably a tungsten plug. The plug is formed concurrent with the conventional contact and first metal wiring processing of the DRAM. The contact is used in DRAM test arrays for characterizing the quality of MOSFET gate insulator as well as the performance characteristics of the MOSFET itself. Connection to the conductive plug is made with first metal wiring. The test structures can be built at any position within the array and since they are located above the polysilicon bitline/wordline structure, the metal connection lines for the contacts do not interfere with the structure of the test array itself other than the sacrifice of the test cell from the array. Multiple devices may be designated from anywhere in the array, and probe contacts may be conveniently located on the chip.

摘要翻译： 描述了用于在层叠电容器DRAM单元中形成与MOSFET的漏极的欧姆接触的结构。 通过在电池电容器的上电池板中形成开口形成接触，并通过该开口与存储板与导电插塞（优选为钨插塞）接触。 插头与DRAM的常规触点和第一金属布线处理同时形成。 该触点用于DRAM测试阵列，用于表征MOSFET栅极绝缘体的质量以及MOSFET本身的性能特性。 与导电插头的连接由第一金属布线制成。 测试结构可以建立在阵列内的任何位置，并且由于它们位于多晶硅位线/字线结构之上，所以触点的金属连接线不会干扰测试阵列本身的结构，而不是测试的牺牲 单元格从数组。 可以从阵列中的任何地方指定多个器件，并且探针触点可以方便地位于芯片上。

公开(公告)号：US5877092A

公开(公告)日：1999-03-02

申请号：US877985

申请日：1997-06-18

申请人： Shing-Long Lee ,  Julie Huang

发明人： Shing-Long Lee ,  Julie Huang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/31105 ,  H01L21/76804

摘要： A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

摘要翻译： 描述了一种方法，其使用两种不同种类的顺序沉积的氧化硅层的差分蚀刻行为以及受控的厚度和蚀刻条件，以允许蚀刻诸如通孔接触孔，氧化物侧壁和交叉绝缘边缘之类的特征， - 突破阶梯高度轮廓，以实现更好的边缘覆盖，同时仍然保持紧密附着在相邻特征之间的最小间距设计基准规则。

公开(公告)号：US5946569A

公开(公告)日：1999-08-31

申请号：US755871

申请日：1996-12-02

申请人： Julie Huang

发明人： Julie Huang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/70

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L28/91 ,  H01L27/10852 ,  Y10S438/97

摘要： A method of removing an etch-stop layer such as Si.sub.3 N.sub.4 from the vicinity of contact openings is described. A need for the removal of this material arises when the surface of the etch-stop layer is exposed during processing and the substrate is subjected to temperatures above 700.degree. C. Because of the high intrinsic interfacial stress residing in the Si.sub.3 N.sub.4, the thermal impact causes cracks in the layer which emanate from the corners of the contact openings and travel, with branching, over a considerable distance from the opening. These cracks are prone to moisture adsorption and contamination which can compromise the reliability and performance of contacts. In addition, where contact openings are formed through insulating layers having an intermediate etch-stop layer, protrusions of the etch-stop layer occur within the contact opening because of un-even etching. These protrusions shadow the flux of subsequently deposited barrier materials into the opening, thereby forming weak spots along the contact walls. Timely removal the etch-stop layer around the contact opening eliminates these protrusions.

摘要翻译： 描述了从接触开口附近去除诸如Si 3 N 4的蚀刻停止层的方法。 当在加工过程中暴露蚀刻停止层的表面并且衬底经受高于700℃的温度时，会出现去除这种材料的需要。由于存在于Si 3 N 4中的高固有界面应力，热冲击导致 该层中的裂纹从接触开口的角落发出并且与分支相距离开口相当远的距离行进。 这些裂缝容易受到吸湿和污染，这可能会影响触点的可靠性和性能。 此外，当通过具有中间蚀刻停止层的绝缘层形成接触开口时，由于不均匀蚀刻，蚀刻停止层的突起出现在接触开口内。 这些突起将随后沉积的阻挡材料的焊剂遮蔽到开口中，从而沿接触壁形成弱点。 及时移除接触开口周围的蚀刻停止层消除了这些突起。

公开(公告)号：US5943582A

公开(公告)日：1999-08-24

申请号：US851115

申请日：1997-05-05

申请人： Julie Huang ,  Shing-Long Lee

发明人： Julie Huang ,  Shing-Long Lee

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/87 ,  H01L28/91

摘要： The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

摘要翻译： 本发明公开了一种用于形成DRAM堆叠电容器的方法，该方法通过利用致密氧化物层作为用于形成层叠电容器的接触孔的上氧化层的湿式蚀刻工艺的蚀刻停止层，从而不需要硅 氮化物蚀刻停止层和在这种堆叠电容器形成过程中通常观察到的许多处理困难的发生。 低氧化物层可以通过BPTEOS化学形成，而上部氧化物层可以通过臭氧-TEOS化学形成。

公开(公告)号：US06184076B2

公开(公告)日：2001-02-06

申请号：US09345354

申请日：1999-07-01

申请人： Julie Huang

发明人： Julie Huang

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/91 ,  Y10S438/97

摘要： A method of removing an etch-stop layer such as Si3N4 from the vicinity of contact openings is described. A need for the removal of this material arises when the surface of the etch-stop layer is exposed during processing and the substrate is subjected to temperatures above 700° C. Because of the high intrinsic interfacial stress residing in the Si3N4, the thermal impact causes cracks in the layer which emanate from the corners of the contact openings and travel, with branching, over a considerable distance from the opening. These cracks are prone to moisture adsorption and contamination which can compromise the reliability and performance of contacts. In addition, where contact openings are formed through insulating layers having an intermediate etch-stop layer, protrusions of the etch-stop layer occur within the contact opening because of un-even etching. These protrusions shadow the flux of subsequently deposited barrier materials into the opening, thereby forming weak spots along the contact walls. Timely removal the etch-stop layer around the contact opening eliminates these protrusions.

摘要翻译： 描述了从接触开口附近去除诸如Si 3 N 4的蚀刻停止层的方法。 当在加工过程中暴露蚀刻停止层的表面并且使衬底经受高于700℃的温度时，需要去除这种材料。由于存在于Si 3 N 4中的高固有界面应力，热冲击 该层中的裂纹从接触开口的角落发出并且与分支相距离开口相当远的距离行进。 这些裂缝容易受到吸湿和污染，这可能会影响触点的可靠性和性能。 此外，当通过具有中间蚀刻停止层的绝缘层形成接触开口时，由于不均匀蚀刻，蚀刻停止层的突起出现在接触开口内。 这些突起将随后沉积的阻挡材料的焊剂遮蔽到开口中，从而沿接触壁形成弱点。 及时移除接触开口周围的蚀刻停止层消除了这些突起。