公开(公告)号：US4744056A

公开(公告)日：1988-05-10

申请号：US835081

申请日：1986-02-28

申请人： James Yu ,  Hong-Gee Fang ,  Moon-Yee Wang ,  Robin W. Cheung

发明人： James Yu ,  Hong-Gee Fang ,  Moon-Yee Wang ,  Robin W. Cheung

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/1112 ,  G11C11/412 ,  Y10S257/904

摘要： The substrate active region contains the source and drain regions for the transistors in each cell. The grounded drains of the two pulldown transistors extend symmetrically into the three adjacent cells coupling with six other pulldown drains. This common ground node has a single upward contact to the metal ground lead. The poly-2 has a similar voltage node coupling eight pulldown resistors in four adjacent cells to the metal Vdd lead. The poly-2 forming the lightly doped resistor area has a heavily doped conductive area at each end for coupling the resistor into the pulldown circuit. The pulldown gate bands have 45 degree bends to maximize the gate area relative to the pass gate area. The gate bends cooperate with corresponding 45 degree slants in the edges of the active region to minimize the effect of misalignment. A conductive poly word line forms the pass gates just above the active region. A metal word line connects periodically with the poly word line to minimize the effect of the distributive resistance of poly. Poly-2 is used to build up the contact from the drains of the pass transistor in the substrate active region to the metal bit leads. The lateral spread of the contact aperture is limited leaving a marging of insulating oxide between the bit contact and the pass gate structure.

摘要翻译： 衬底有源区域包含每个单元中的晶体管的源极和漏极区域。 两个下拉晶体管的接地漏极对称地延伸到与六个其它下拉漏极耦合的三个相邻的单元中。 该公共接地节点具有与金属接地线的单个向上接触。 poly-2具有与金属Vdd导联的四个相邻单元中的八个下拉电阻耦合的类似电压节点。 形成轻掺杂电阻区域的poly-2在每个端部具有重掺杂的导电区域，用于将电阻器耦合到下拉电路中。 下拉栅极带具有45度弯曲，以使相对于通过栅极区域的栅极面积最大化。 门弯曲与有源区域的边缘中的相应的45度倾斜相配合，以最小化未对准的影响。 导电多晶字线形成恰好在有源区上方的通孔。 金属字线与多字线周期性地连接，以最小化聚合物的分布电阻的影响。 Poly-2用于建立从衬底有源区中的传输晶体管的漏极到金属位引线的接触。 接触孔的横向扩展受到限制，在位接触和通过门结构之间留下绝缘氧化物的边缘。

公开(公告)号：US4754434A

公开(公告)日：1988-06-28

申请号：US770815

申请日：1985-08-28

申请人： Moon-Yee Wang ,  James Yu ,  Hong-Gee Fang

发明人： Moon-Yee Wang ,  James Yu ,  Hong-Gee Fang

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.

摘要翻译： 一种存储器，包括用于选择存储器单元的冗余行的装置，其中耦合到第一组位线的存储器单元的有缺陷的常规行的寻址导致选择耦合到第二组位线的冗余行的存储器单元， 避免了由于在存储器中同时使能两条字线引起的信号干扰。

公开(公告)号：US4888731A

公开(公告)日：1989-12-19

申请号：US193308

申请日：1988-05-11

申请人： Patrick T. Chuang ,  Robert L. Yau ,  Hiroshi Yoshida ,  Moon-Yee Wang

发明人： Patrick T. Chuang ,  Robert L. Yau ,  Hiroshi Yoshida ,  Moon-Yee Wang

IPC分类号： G11C15/04 ,  G06F17/30

CPC分类号： G06F17/30982

摘要： A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.

公开(公告)号：US6157939A

公开(公告)日：2000-12-05

申请号：US90798

申请日：1998-06-04

申请人： Chuong Van Vo ,  Moon-Yee Wang

发明人： Chuong Van Vo ,  Moon-Yee Wang

IPC分类号： G06F7/52

CPC分类号： G06F7/5338

摘要： An multiplier circuit that generates a negate product -B*C quickly without requiring a separate negate operation. This multiplier circuit uses partial product multiplication and any of a variety of multiplication techniques, such as bit-pair recoding or the Booth algorithm, to perform multiplication and negate multiplication operations. The multiplier circuit uses an encoder circuit to produce encoded multiplier strings in accordance with such multiplication techniques. The multiplier circuit reorders bits of such encoded multiplier strings to cause a binary multiplier circuit to generate the negate product -B*C rather than the product B*C. The reordering can be accomplished in any manner, such as by a bus coupling the encoder circuit to the binary multiplier circuit. The encoder circuit can be coupled to the binary multiplier circuit using two buses and a multiplexor circuit. One bus might reorder the bits of the encoded multiplier strings to cause the binary multiplier circuit to produce the negate product -B*C and the other bus might pass the encoded multiplier strings to the binary multiplier circuit without reordering its bits so that the binary multiplier circuit produces the product B*C. The multiplexor may be used to select one of these two buses depending upon which product is desired. This multiplier circuit might be used in a circuit that performs a multiply/add calculation to produce the result A+B*C and that performs a multiply/subtract calculation to produce the result A-B*C.

摘要翻译： 一个乘法器电路，可以快速生成一个负值产品-B * C，而不需要单独的否定运算。 该乘法器电路使用部分乘积乘法和诸如位对重新编码或布斯算法的各种乘法技术中的任何一种执行乘法和否定乘法运算。 乘法器电路使用编码器电路根据这种乘法技术产生编码乘法器串。 乘法器电路对这些编码乘法器串的位进行重新排序，以使二进制乘法电路产生否定乘积-B * C而不是乘积B * C。 重新排序可以以任何方式完成，例如通过将编码器电路耦合到二进制乘法器电路的总线。 编码器电路可以使用两个总线和多路复用器电路耦合到二进制乘法器电路。 一个总线可能会重新排序编码的乘法器串的位，以使二进制乘法器电路产生否定乘积-B * C，而另一个总线可以将编码的乘法器串传递到二进制乘法器电路，而不对其位进行重新排序，使得二进制乘法器 电路产生产品B * C。 根据期望的产品，多路复用器可用于选择这两条总线中的一条。 该乘法器电路可以用于执行乘/加计算以产生结果A + B * C的电路，并且执行乘/减计算以产生结果A-B * C。

公开(公告)号：US4928260A

公开(公告)日：1990-05-22

申请号：US193315

申请日：1988-05-11

申请人： Patrick T. Chuang ,  Robert L. Yau ,  Hiroshi Yoshida ,  Moon-Yee Wang

发明人： Patrick T. Chuang ,  Robert L. Yau ,  Hiroshi Yoshida ,  Moon-Yee Wang

IPC分类号： G06F17/30 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G11C15/04

摘要： A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.

公开(公告)号：US4890260A

公开(公告)日：1989-12-26

申请号：US193312

申请日：1988-05-11

申请人： Patrick T. Chuang ,  Robert L. Yau ,  Hiroshi Yoshida ,  Moon-Yee Wang

发明人： Patrick T. Chuang ,  Robert L. Yau ,  Hiroshi Yoshida ,  Moon-Yee Wang

IPC分类号： G06F17/30 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G11C15/04

摘要： A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If a skip bit is detected in any one of the words, that word containing the detected skip bit is eliminated from the search.Each word in the array also contains an empty bit which is used to indicate an empty word location in the array. When all empty bits are set, the array is automatically reset to empty or zero.