公开(公告)号：US4744056A

公开(公告)日：1988-05-10

申请号：US835081

申请日：1986-02-28

申请人： James Yu ,  Hong-Gee Fang ,  Moon-Yee Wang ,  Robin W. Cheung

发明人： James Yu ,  Hong-Gee Fang ,  Moon-Yee Wang ,  Robin W. Cheung

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/1112 ,  G11C11/412 ,  Y10S257/904

摘要： The substrate active region contains the source and drain regions for the transistors in each cell. The grounded drains of the two pulldown transistors extend symmetrically into the three adjacent cells coupling with six other pulldown drains. This common ground node has a single upward contact to the metal ground lead. The poly-2 has a similar voltage node coupling eight pulldown resistors in four adjacent cells to the metal Vdd lead. The poly-2 forming the lightly doped resistor area has a heavily doped conductive area at each end for coupling the resistor into the pulldown circuit. The pulldown gate bands have 45 degree bends to maximize the gate area relative to the pass gate area. The gate bends cooperate with corresponding 45 degree slants in the edges of the active region to minimize the effect of misalignment. A conductive poly word line forms the pass gates just above the active region. A metal word line connects periodically with the poly word line to minimize the effect of the distributive resistance of poly. Poly-2 is used to build up the contact from the drains of the pass transistor in the substrate active region to the metal bit leads. The lateral spread of the contact aperture is limited leaving a marging of insulating oxide between the bit contact and the pass gate structure.

摘要翻译： 衬底有源区域包含每个单元中的晶体管的源极和漏极区域。 两个下拉晶体管的接地漏极对称地延伸到与六个其它下拉漏极耦合的三个相邻的单元中。 该公共接地节点具有与金属接地线的单个向上接触。 poly-2具有与金属Vdd导联的四个相邻单元中的八个下拉电阻耦合的类似电压节点。 形成轻掺杂电阻区域的poly-2在每个端部具有重掺杂的导电区域，用于将电阻器耦合到下拉电路中。 下拉栅极带具有45度弯曲，以使相对于通过栅极区域的栅极面积最大化。 门弯曲与有源区域的边缘中的相应的45度倾斜相配合，以最小化未对准的影响。 导电多晶字线形成恰好在有源区上方的通孔。 金属字线与多字线周期性地连接，以最小化聚合物的分布电阻的影响。 Poly-2用于建立从衬底有源区中的传输晶体管的漏极到金属位引线的接触。 接触孔的横向扩展受到限制，在位接触和通过门结构之间留下绝缘氧化物的边缘。

公开(公告)号：US4754434A

公开(公告)日：1988-06-28

申请号：US770815

申请日：1985-08-28

申请人： Moon-Yee Wang ,  James Yu ,  Hong-Gee Fang

发明人： Moon-Yee Wang ,  James Yu ,  Hong-Gee Fang

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.

摘要翻译： 一种存储器，包括用于选择存储器单元的冗余行的装置，其中耦合到第一组位线的存储器单元的有缺陷的常规行的寻址导致选择耦合到第二组位线的冗余行的存储器单元， 避免了由于在存储器中同时使能两条字线引起的信号干扰。

公开(公告)号：US07158400B2

公开(公告)日：2007-01-02

申请号：US10711938

申请日：2004-10-14

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Ching-Tang Wu

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Ching-Tang Wu

IPC分类号： G11C11/24

CPC分类号： G11C11/4076 ,  G11C11/404

摘要： A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

摘要翻译： 公开了使用位线和位线条操作动态随机存取存储器（DRAM）的方法。 DRAM通过使用经由开关装置耦合到位线的电荷存储装置来存储数据。 开关器件接通时会发生电压降。 该方法响应于由于电压降而导致的功率电压降低，以第一电压或零电压对电荷存储装置进行编程。 为了访问数据，位线和位线条被充电到电源电压，开关器件导通，并且存储在电荷存储器件中的数据根据​​位线和位线之间的电压差来确定 酒吧。

公开(公告)号：US20060023487A1

公开(公告)日：2006-02-02

申请号：US10711938

申请日：2004-10-14

申请人： Hong-Gee Fang ,  Wen-Chieh Lee

发明人： Hong-Gee Fang ,  Wen-Chieh Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/4076 ,  G11C11/404

摘要： A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

摘要翻译： 公开了使用位线和位线条操作动态随机存取存储器（DRAM）的方法。 DRAM通过使用经由开关装置耦合到位线的电荷存储装置来存储数据。 开关器件接通时会发生电压降。 该方法响应于由于电压降而导致的功率电压降低，以第一电压或零电压对电荷存储装置进行编程。 为了访问数据，位线和位线条被充电到电源电压，开关器件导通，并且存储在电荷存储器件中的数据根据​​位线和位线之间的电压差来确定 酒吧。

公开(公告)号：US20060004954A1

公开(公告)日：2006-01-05

申请号：US10880581

申请日：2004-07-01

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C2211/4061

摘要： A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

摘要翻译： 一种用于操作存储器件的方法，包括周期性地产生用于执行刷新操作的刷新请求信号，提供用于执行访问操作的访问请求信号，如果刷新请求信号在访问请求信号之前发生，则执行刷新操作;以及 如果访问请求信号在刷新请求信号之前发生，则执行访问操作。

公开(公告)号：US07433996B2

公开(公告)日：2008-10-07

申请号：US10880581

申请日：2004-07-01

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C2211/4061

摘要： A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

摘要翻译： 一种用于操作存储器件的方法，包括周期性地产生用于执行刷新操作的刷新请求信号，提供用于执行访问操作的访问请求信号，如果刷新请求信号在访问请求信号之前发生，则执行刷新操作;以及 如果访问请求信号在刷新请求信号之前发生，则执行访问操作。

公开(公告)号：US07113439B2

公开(公告)日：2006-09-26

申请号：US10829207

申请日：2004-04-22

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

IPC分类号： G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

摘要： A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

摘要翻译： 一种操作包括以行和列形成的单元阵列的存储器件的方法，所述存储器件包括提供控制信号，激活所述控制信号，所述激活的控制信号包括第一状态和第二状态，响应于所述第一状态和第二状态连续执行访问周期 在一段时间内激活的控制信号的第一状态，并且在该周期的另一部分中响应于激活的控制信号的第二状态连续地执行刷新周期。

公开(公告)号：US5856947A

公开(公告)日：1999-01-05

申请号：US920604

申请日：1997-08-27

申请人： Hong-Gee Fang

发明人： Hong-Gee Fang

IPC分类号： G11C11/401 ,  G06F12/06 ,  G11C7/10 ,  G11C16/04

CPC分类号： G11C7/1042

摘要： An integrated circuit includes a controller and a memory to implement a graphics controller. The controller and memory are controlled by a common clock signal to operate synchronously with each other. The memory is organized in a plurality of storage arrays, organized in two banks. A set of bit-line sense amplifiers is provided for each bank. A pair of row decoders decode a row address to select a row of data from each bank. The selected row of data is received by a pair of bit-line sense amplifiers. A column decoder selects a column of data from the pair of bit-line sense amplifiers. A pair of multiplexers select one-half of the selected column in response to a HI/LO signal and then select the remaining half of the selected data in response to a change in value of the HI/LO signal. Main or data sense amplifiers amplify the output of the multiplexers to provide data outputs in the form of full swing signals.

摘要翻译： 集成电路包括控制器和用于实现图形控制器的存储器。 控制器和存储器由公共时钟信号控制，以彼此同步操作。 存储器被组织在由两个组合组成的多个存储阵列中。 为每个存储体提供一组位线读出放大器。 一行行解码器解码行地址以从每个行选择一行数据。 所选择的数据行由一对位线读出放大器接收。 列解码器从一对位线读出放大器中选择一列数据。 一对多路复用器响应于HI / LO信号选择所选列的一半，然后响应于HI / LO信号的值的改变选择所选数据的剩余一半。 主或数据读出放大器放大多路复用器的输出以提供全速信号形式的数据输出。

公开(公告)号：US20050237836A1

公开(公告)日：2005-10-27

申请号：US10829207

申请日：2004-04-22

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu ,  Ching-Wen Chen

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

摘要： A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

摘要翻译： 一种操作包括以行和列形成的单元阵列的存储器件的方法，所述存储器件包括提供控制信号，激活所述控制信号，所述激活的控制信号包括第一状态和第二状态，响应于所述第一状态和第二状态连续执行访问周期 在一段时间内激活的控制信号的第一状态，并且在该周期的另一部分中响应于激活的控制信号的第二状态连续地执行刷新周期。

公开(公告)号：US20050040895A1

公开(公告)日：2005-02-24

申请号：US10710764

申请日：2004-08-02

申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Chih-Yuan Cheng

发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Chih-Yuan Cheng

IPC分类号： H03B5/24 ,  H03K3/012 ,  H03K3/03 ,  H03L7/00

CPC分类号： H03K3/0315 ,  H03K3/012

摘要： A low power consumption oscillation circuit and a delay circuit thereof are disclosed. The circuit comprises an enable circuit, an oscillator delay circuit and a feedback control network. The enable circuit is adapted for receiving an enable signal and performing an initial oscillation. The enable circuit outputs an initial oscillation signal according to a feedback control signal. The oscillator delay circuit is coupled to the enable circuit and is adapted for alternately generating a high and a low level oscillation signals according to the initial oscillation signal. The feedback control network is coupled to the oscillator delay circuit and is adapted for integrating the high and the low level oscillation signals to generate a feedback control signal and outputting the feedback control signal to the enable the circuit for activating next oscillation.

摘要翻译： 公开了一种低功耗振荡电路及其延迟电路。 该电路包括使能电路，振荡器延迟电路和反馈控制网络。 使能电路适于接收使能信号并执行初始振荡。 使能电路根据反馈控制信号输出初始振荡信号。 振荡器延迟电路耦合到使能电路，适用于根据初始振荡信号交替产生高电平和低电平的振荡信号。 反馈控制网络耦合到振荡器延迟电路，适用于对高电平和低电平振荡信号进行积分以产生反馈控制信号，并将反馈控制信号输出到启动下一个振荡电路。