公开(公告)号：US5134309A

公开(公告)日：1992-07-28

申请号：US534614

申请日：1990-06-07

申请人： Motoaki Matsumoto ,  Hideaki Kimura

发明人： Motoaki Matsumoto ,  Hideaki Kimura

IPC分类号： H03K5/02 ,  H03K5/12 ,  H03K5/1252

CPC分类号： H03K5/1252 ,  H03K5/02 ,  H03K5/12

摘要： A preamplifier providing adequate boost even to weak and small input currents, and thus achieving favorable gain and signal-to-noise ratio. An input current is converted to a voltage, which is provided to a differential amplification section. A phase-adjusted version of that voltage signal also is provided to the differential amplifier, the differential amplifier thus outputting an amplified signal based on the phase difference between its inputs. The preamplifier may be incorporated on a single chip, using MOS transistors or gallium arsenide techniques. A level clamping device may be provided in the event that the input current exceeds a predetermined value. The inventive preamplifier also may be incorporated advantageously into a waveform shaping circuit.

摘要翻译： 一个前置放大器即使对弱和小的输入电流也能提供足够的增益，从而获得良好的增益和信噪比。 输入电流被转换成提供给差分放大部分的电压。 该电压信号的相位调整版本也被提供给差分放大器，因此差分放大器基于其输入之间的相位差输出放大的信号。 前置放大器可以使用MOS晶体管或砷化镓技术结合在单个芯片上。 在输入电流超过预定值的情况下，可以提供电平钳位装置。 本发明的前置放大器还可以有利地并入到波形整形电路中。

公开(公告)号：US4956688A

公开(公告)日：1990-09-11

申请号：US374570

申请日：1989-06-27

申请人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： H01L27/102 ,  H01L29/732

CPC分类号： H01L27/1025 ,  H01L29/7327

摘要： A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有高抗免除由α射线引起的软误差的结构的双极记忆。 触发器的晶体管，即存储单元的基本电路被反转，并且其负载装置具有用于屏蔽触发器与基板内产生的噪声的屏蔽装置。 采用pnp型晶体管或肖特基势垒二极管作为负载器件。 在设置有器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层。 跨越掩埋层和掺杂层施加反向偏压，以切断衬底内产生的噪声。

公开(公告)号：US4858184A

公开(公告)日：1989-08-15

申请号：US42698

申请日：1987-04-27

申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： G11C11/411

CPC分类号： G11C11/4113 ,  G11C11/4116

摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。

公开(公告)号：US5448188A

公开(公告)日：1995-09-05

申请号：US223303

申请日：1994-04-04

申请人： Motoaki Matsumoto ,  Yoshihiko Sato

发明人： Motoaki Matsumoto ,  Yoshihiko Sato

IPC分类号： H03F3/72 ,  H04N5/265 ,  H04N5/445 ,  H03K5/24

CPC分类号： H04N5/265 ,  H03F3/72 ,  H04N5/445

摘要： A signal processing device for selectively producing as an output signal either a signal corresponding to an input signal r a signal which may be a fixed voltage level for muting purposes or a mixed signal. A current switch composed of pairs of differential transistors switches Among a plurality of current paths in accordance with a difference between the voltage levels of a pair of input signals varying in level in phase opposition to each other, or in accordance with a difference between the voltage levels of a reference voltage and a signal phase input signal. A load circuit composed of a plurality of resistors is connected in series with one of the current paths. A current bypass forming circuit which forms a current bypass of a constant current at a desired timing corresponding to a pulse signal with respect to the current path forming the load circuit effects the generation of an output signal not corresponding to the input signal, that is, a fixed voltage for muting the mixed signal.

摘要翻译： 信号处理装置，用于选择性地产生对应于输入信号r的信号作为输出信号，信号可以是用于静音目的的固定电压电平或混合信号。 由一对差分晶体管开关构成的电流开关根据在相位相反的电平变化的一对输入信号的电压电平之间的差异，或者根据电压 参考电压和信号相位输入信号的电平。 由多个电阻器组成的负载电路与电流路径之一串联连接。 在与形成负载电路的电流路径相对应的脉冲信号的期望定时处形成恒定电流的电流旁路的电流旁路形成电路实现不对应于输入信号的输出信号的产生， 用于使混合信号静音的固定电压。

公开(公告)号：US4958320A

公开(公告)日：1990-09-18

申请号：US361633

申请日：1989-06-02

申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： G11C11/411 ,  H01L27/102

CPC分类号： G11C11/4113 ,  G11C11/4116 ,  H01L27/1025

摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。