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    COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY
    6.
    发明申请
    COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY 有权
    BICMOS技术中收集双极接头晶体管

    公开(公告)号：US20140231877A1

    公开(公告)日：2014-08-21

    申请号：US13769500

    申请日：2013-02-18

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

    IPC分类号： H01L29/66 ,  H01L29/737

    CPC分类号： H01L29/7371 ,  H01L29/0649 ,  H01L29/267 ,  H01L29/66242 ,  H01L29/7327 ,  H01L29/737 ,  H01L29/7378

    摘要： Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

    摘要翻译： 双极结晶体管的制造方法，器件结构和设计结构。 在衬底中限定的器件区域中形成发射极。 在发射极上形成一个本征基极。 形成了通过内在基极与发射极分离的集电极。 集电体包括具有大于器件区域的半导体材料的电子带隙的电子带隙的半导体材料。

    Integrated Circuit Devices with Well Regions and Methods for Forming the Same
    7.
    发明申请
    Integrated Circuit Devices with Well Regions and Methods for Forming the Same 审中-公开
    具有井区的集成电路器件及其形成方法

    公开(公告)号：US20140001518A1

    公开(公告)日：2014-01-02

    申请号：US13539027

    申请日：2012-06-29

    申请人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

    发明人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

    IPC分类号： H01L27/07 ,  H01L21/8249

    CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/07 ,  H01L27/085 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/732 ,  H01L29/7327 ,  H01L29/808 ,  H01L29/861 ,  H01L29/93

    摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

    摘要翻译： 一种方法包括在衬底中形成第一导电类型的深阱区域，注入深阱区域的一部分以形成第一栅极，以及植入深阱区域以形成阱区域。 阱区和第一栅极是与第一导电类型相反的第二导电类型。 执行注入以在第一栅极上形成第一导电类型的沟道区。 植入覆盖沟道区域的深阱区域的一部分以形成第二导电类型的第二栅极。 进行源极/漏极注入以在第二栅极的相对侧上形成第一导电类型的源极区域和漏极区域。 源极和漏极区域连接到沟道区域，并且与沟道区域和第一栅极重叠。

    Transistor configuration for a bandgap circuit
    8.
    发明申请
    Transistor configuration for a bandgap circuit 失效
    晶体管配置用于带隙电路

    公开(公告)号：US20030030128A1

    公开(公告)日：2003-02-13

    申请号：US10217184

    申请日：2002-08-12

    发明人： Helmut Fischer ,  Jurgen Lindolf

    IPC分类号： G05F001/10 ,  H01L031/0256 ,  H01L027/102 ,  H01L029/70 ,  H01L027/082

    CPC分类号： G05F3/30 ,  H01L29/7327

    摘要： A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

    摘要翻译： 用于带隙电路的晶体管配置被配置为npn晶体管的形式。 被埋置的n型阱包围的绝缘p型阱用作基极端子。 n型阱构成发射极端子。 在p型阱中形成用作集电极端子的负掺杂区域。 所使用的结构存在于DRAM工艺中，因此可用于在带隙电路中形成npn晶体管作为覆盖二极管。

    Heterojunction avalanche transistor
    9.
    发明授权
    Heterojunction avalanche transistor 失效
    异质结雪崩晶体管

    公开(公告)号：US5036372A

    公开(公告)日：1991-07-30

    申请号：US579681

    申请日：1990-09-10

    申请人： Toshiyuki Ohishi ,  Yuji Abe ,  Hiroshi Sugimoto ,  Ken-ichi Ohisuka ,  Teruhito Matsui

    发明人： Toshiyuki Ohishi ,  Yuji Abe ,  Hiroshi Sugimoto ,  Ken-ichi Ohisuka ,  Teruhito Matsui

    IPC分类号： H01L29/68 ,  H01L29/205 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L29/7327 ,  H01L29/7313

    摘要： An avalanche transistor has a heterojunction emitter-base junction. The avalanche transistor includes a spacer layer provided between an emitter layer and a base layer. The spacer layer has an energy band gap between that of the base layer and that of the emitter layer, a carrier concentration lower than that of the base layer, and a thickness so that the whole spacer layer becomes a depletion layer at thermal equillibrium so that a neutral region is produced in the spacer layer at a voltage lower than the threshold voltage of the emitter-base junction. Thus, the same element is both bistable with the base current as a parameter and has an S-shaped negative differential resistance with the base voltage as a parameter.

    摘要翻译： 雪崩晶体管具有异质结发射极 - 基极结。 雪崩晶体管包括设置在发射极层和基极层之间的间隔层。 间隔层在基底层和发射极层之间的能带隙，载流子浓度低于基底层的载流子浓度和厚度，使得整个间隔层成为热平衡的耗尽层，使得 在间隔层中以低于发射极 - 基极结的阈值电压的电压产生中性区。 因此，相同的元件与基极电流作为参数都是双稳态的，并且具有基极电压作为参数的S形负差分电阻。