公开(公告)号：US06374205B1

公开(公告)日：2002-04-16

申请号：US09248989

申请日：1999-02-12

申请人： Mototaka Kuribayashi ,  Masaaki Yamada ,  Hideki Takeuchi

发明人： Mototaka Kuribayashi ,  Masaaki Yamada ,  Hideki Takeuchi

IPC分类号： G06F9455

CPC分类号： G06F17/5036

摘要： A method reduces circuit data to be simulated, by extracting element data that influences a result of simulation out of the circuit data, thereby shortening a simulation time while maintaining the accuracy of simulation. Also provided is a simulation method that employs the reduction method. The method includes the steps of entering one of an input vector and/or an observation point for the circuit data to be simulated, and extracting an element data corresponding to a node influenced by propagation of a varying state of the input signal, the varying state for the node having an influence for the observation point, from the circuit data according to the input vector and/or observation point. The extracted nodes and elements related thereto are used to prepare reduced circuit data that is simulated. The method reduces the scale of a circuit to simulate by extracting only essential elements that affect a result of simulation from circuit data such as a netlist that forms the circuit to be simulated.

摘要翻译： 通过提取影响电路数据中的模拟结果的元素数据，减少模拟电路数据，从而缩短模拟时间，同时保持模拟精度。 还提供了采用还原方法的模拟方法。 该方法包括以下步骤：输入要被仿真的电路数据的输入矢量和/或观测点之一，以及提取与由输入信号的变化状态的传播影响的节点对应的元素数据，变化状态 对于具有对观察点的影响的节点，根据输入向量和/或观察点的电路数据，提取的节点和与其相关的元素用于准备被模拟的简化电路数据。 该方法通过从诸如形成要仿真的电路的网表等电路数据中提取仅影响仿真结果的基本元素来减小模拟电路的规模。

公开(公告)号：US06223333B1

公开(公告)日：2001-04-24

申请号：US08882495

申请日：1997-06-25

申请人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

发明人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

摘要翻译： 在定时分析方法中，连接信息在读取电路的连接信息之后，预先与存储在存储器中的电路图案进行比较，连接信息补充处理用于补充垂直电路关于匹配电路图案的连接信息 当连接信息与注册的电路图案中的一个匹配时执行存储的连接信息，并且执行已经由连接信息补充处理补充的连接信息的定时分析。

公开(公告)号：US5966521A

公开(公告)日：1999-10-12

申请号：US853908

申请日：1997-05-09

申请人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

发明人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5031

摘要： The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required. A static-timing analysis technique according to the present invention comprises a net-list input step S110 which inputs per-transistor basis connection information, to construct an internal data structure for analysis; an expected-value check step S120 which checks, against the above-mentioned internal data structure, each node on whether its expected values may be a high-impedance state; a signal-flow direction narrow-down step S130 which narrows down the directions in which the transistor signal may flow, based on the obtained expected values; a division step S140 which divides a sequential circuit into units consisting of only combinational sub-circuits; a path search step S150 which searches paths for each of thus divided units; and an output step S170 which outputs the obtained results.

摘要翻译： 本发明提供了一种用于分析LSI的静态定时的系统和方法，其涉及输出结果中包含的少量虚路径，并且还减少了所需的处理时间。 根据本发明的静态时序分析技术包括输入每晶体管基连接信息的网络列表输入步骤S110，以构建用于分析的内部数据结构; 预测值检查步骤S120，其针对上述内部数据结构检查每个节点关于其预期值是否可能是高阻抗状态; 基于所获得的期望值，使晶体管信号可能流过的方向变窄的信号流动方向缩小步骤S130; 将顺序电路分为仅由组合子电路组成的单元的分割步骤S140; 路径搜索步骤S150，其针对每个这样划分的单元的路径进行搜索; 以及输出步骤S170，其输出所获得的结果。

公开(公告)号：US5583788A

公开(公告)日：1996-12-10

申请号：US427979

申请日：1995-04-21

申请人： Mototaka Kuribayashi

发明人： Mototaka Kuribayashi

IPC分类号： H01L21/82 ,  G06F17/50 ,  G06F15/00

CPC分类号： G06F17/5077 ,  Y10S257/923

摘要： A method, according to a hierarchical processing used for a computer-aided design system, for automatically wiring a circuit by dividing a region into a plurality of coarse global grids. The automatic wiring method includes the steps of: setting up and calculating an evaluation function having therein a plurality of evaluation terms for indicating selectability by which the cut-line is preferentially selected so that a wiring congestion is most relaxed; giving weights to the respective plurality of evaluation terms and defining an evaluation function which totals the plurality of the evaluation terms; dividing the region into two by a cut-line having a minimum value in the evaluation functions; determining a position to cross all nets crossing the cut-line; and performing the above steps recursively and hierarchically until the divided regions become a predetermined minimum size.

摘要翻译： 根据用于计算机辅助设计系统的分级处理，通过将区域划分成多个粗大的全局网格来自动布线电路的方法。 自动布线方法包括以下步骤：建立和计算其中具有多个评估项的评估函数，用于指示优选地选择切割线的选择性，使得布线拥塞最松弛; 给予相应的多个评估项的权重并定义总计多个评估项的评估函数; 通过评估函数中具有最小值的切割线将该区域划分为两个; 确定跨过所有切割线的网络的位置; 并递归地和分层地执行上述步骤，直到划分的区域变为预定的最小尺寸。

公开(公告)号：US5012427A

公开(公告)日：1991-04-30

申请号：US303261

申请日：1989-01-30

申请人： Mototaka Kuribayashi

发明人： Mototaka Kuribayashi

IPC分类号： G06F1/04 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F1/04

摘要： A semiconductor integrated circuit device comprises a plurality of cell arrays including at least one cell array having main and one feed-through cells, and a plurality of clock driver cells provided on the cell arrays. The feed-through cells are selectively connected to the clock driver cells so that loads imposed to the clock driver cells are made substantially uniform.

摘要翻译： 半导体集成电路器件包括多个单元阵列，其包括至少一个具有主和一个馈通单元的单元阵列，以及设置在单元阵列上的多个时钟驱动单元。 馈通单元选择性地连接到时钟驱动器单元，使得施加到时钟驱动器单元的负载基本上是均匀的。