METHOD AND APPARATUS FOR REDUCING HOST OVERHEAD IN A SOCKET SERVER IMPLEMENTATION
    2.
    发明申请
    METHOD AND APPARATUS FOR REDUCING HOST OVERHEAD IN A SOCKET SERVER IMPLEMENTATION 有权
    用于减少插座服务器实现中的主机的方法和装置

    公开(公告)号:US20100023626A1

    公开(公告)日:2010-01-28

    申请号:US12574263

    申请日:2009-10-06

    IPC分类号: G06F15/16

    摘要: A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.

    摘要翻译: 在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。 应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。 使用应用缓冲器,由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。 在传输之后,将完成通知写入主机系统中的两个控制队列之一。 完成通知包括传输的数据的大小和与套接字相关联的标识符。 标识符标识与传送的数据相关联的线程和主机系统中数据的位置。

    Method and apparatus for reducing host overhead in a socket server implementation
    3.
    发明授权
    Method and apparatus for reducing host overhead in a socket server implementation 有权
    减少套接字服务器实现中的主机开销的方法和装置

    公开(公告)号:US07930349B2

    公开(公告)日:2011-04-19

    申请号:US12574263

    申请日:2009-10-06

    IPC分类号: G06F15/16

    摘要: A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.

    摘要翻译: 在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。 应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。 使用应用缓冲器,由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。 在传输之后,将完成通知写入主机系统中的两个控制队列之一。 完成通知包括传输的数据的大小和与套接字相关联的标识符。 标识符标识与传送的数据相关联的线程和主机系统中数据的位置。

    Method and apparatus for reducing host overhead in a socket server implementation
    4.
    发明授权
    Method and apparatus for reducing host overhead in a socket server implementation 有权
    减少套接字服务器实现中的主机开销的方法和装置

    公开(公告)号:US07613813B2

    公开(公告)日:2009-11-03

    申请号:US11225373

    申请日:2005-09-12

    IPC分类号: G06F15/16

    摘要: A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.

    摘要翻译: 在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。 应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。 使用应用缓冲器,由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。 在传输之后,将完成通知写入主机系统中的两个控制队列之一。 完成通知包括传输的数据的大小和与套接字相关联的标识符。 标识符标识与传送的数据相关联的线程和主机系统中数据的位置。

    Messaging with flexible transmit ordering
    5.
    发明授权
    Messaging with flexible transmit ordering 有权
    消息传递灵活的发送顺序

    公开(公告)号:US09596193B2

    公开(公告)日:2017-03-14

    申请号:US13326091

    申请日:2011-12-14

    摘要: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.

    摘要翻译: 在一个实施例中,系统包括分组接收单元。 分组接收单元被配置为接收分组,创建指示多个核中的分组的调度的报头,并且连接报头和分组。 标题是基于数据包的内容。 在一个实施例中,系统包括被配置为存储分组的多个片段的发射仓,所述片段已经被发送到目的地,并且发送仓已经没有收到来自目的地的片段接收的确认。 该系统还包括与发射仓连接的限制验证器。 限制验证器被配置为接收片段并且确定片段是否可以被发送并存储在传送仓中。

    MESSAGING WITH FLEXIBLE TRANSMIT ORDERING
    6.
    发明申请
    MESSAGING WITH FLEXIBLE TRANSMIT ORDERING 有权
    使用灵活的发送订单进行消息传递

    公开(公告)号:US20120155474A1

    公开(公告)日:2012-06-21

    申请号:US13326091

    申请日:2011-12-14

    IPC分类号: H04L12/56

    摘要: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.

    摘要翻译: 在一个实施例中,系统包括分组接收单元。 分组接收单元被配置为接收分组,创建指示多个核中的分组的调度的报头,并且连接报头和分组。 标题是基于数据包的内容。 在一个实施例中,系统包括被配置为存储分组的多个片段的发射仓,所述片段已经被发送到目的地,并且发送仓已经没有收到来自目的地的片段接收的确认。 该系统还包括与发射仓连接的限制验证器。 限制验证器被配置为接收片段并且确定片段是否可以被发送并存储在传送仓中。

    Secure software and hardware association technique
    7.
    发明授权
    Secure software and hardware association technique 有权
    安全的软硬件关联技术

    公开(公告)号:US08677144B2

    公开(公告)日:2014-03-18

    申请号:US12392004

    申请日:2009-02-24

    IPC分类号: G06F21/00

    摘要: In an embodiment, authenticated hardware and authenticated software are cryptographically binded using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. This cryptographic binding technique is referred to herein as secure software and hardware association (SSHA).

    摘要翻译: 在一个实施例中,经认证的硬件和认证的软件使用对称和非对称加密技术被加密地绑定。 加密硬件和软件的密码确保原始设备制造商(OEM)硬件只能运行OEM软件。 加密硬件和软件的加密保护了OEM二进制代码,因此它只能在OEM硬件上运行,不能被复制或更改以对未授权的硬件进行操作。 这种加密绑定技术在这里被称为安全软件和硬件关联(SSHA)。

    SECURE SOFTWARE AND HARDWARE ASSOCIATION TECHNIQUE
    8.
    发明申请
    SECURE SOFTWARE AND HARDWARE ASSOCIATION TECHNIQUE 有权
    安全软件和硬件协会技术

    公开(公告)号:US20090217054A1

    公开(公告)日:2009-08-27

    申请号:US12392004

    申请日:2009-02-24

    IPC分类号: H04L9/06

    摘要: In an embodiment, authenticated hardware and authenticated software are cryptographically binded using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. This cryptographic binding technique is referred to herein as secure software and hardware association (SSHA).

    摘要翻译: 在一个实施例中,经认证的硬件和认证的软件使用对称和非对称加密技术被加密地绑定。 加密硬件和软件的密码确保原始设备制造商(OEM)硬件只能运行OEM软件。 加密硬件和软件的加密保护了OEM二进制代码,因此它只能在OEM硬件上运行,不能被复制或更改以对未授权的硬件进行操作。 这种加密绑定技术在这里被称为安全软件和硬件关联(SSHA)。

    Direct access to low-latency memory
    9.
    发明授权
    Direct access to low-latency memory 有权
    直接访问低延迟内存

    公开(公告)号:US07594081B2

    公开(公告)日:2009-09-22

    申请号:US11024002

    申请日:2004-12-28

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    摘要: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    摘要翻译: 提供内容感知应用处理系统,用于允许定向访问存储在非高速缓冲存储器中的数据,从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器,从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

    IPsec performance optimization
    10.
    发明授权
    IPsec performance optimization 有权
    IPsec性能优化

    公开(公告)号:US07814310B2

    公开(公告)日:2010-10-12

    申请号:US10411967

    申请日:2003-04-12

    IPC分类号: H04L29/06

    摘要: A method and apparatus for optimizing IPsec processing by providing execution units with windowing data during prefetch and managing coherency of security association data by management of security association accesses. Providing execution units with windowing data allows initial parallel processing of IPsec packets. The security association access ordering apparatus serializes access to the dynamic section of security association data according to packet order arrival while otherwise allowing parallel processing of the IPsec packet by multiple execution units in a security processor.

    摘要翻译: 一种通过在预取期间向执行单元提供窗口数据并通过管理安全关联访问来管理安全关联数据的一致性来优化IPsec处理的方法和装置。 为执行单元提供窗口数据允许IPsec数据包的初始并行处理。 安全关联访问排序装置根据分组顺序序列化对安全关联数据的动态部分的访问,而另外允许在安全处理器中由多个执行单元并行处理IPsec分组。