公开(公告)号：US20250098286A1

公开(公告)日：2025-03-20

申请号：US18468556

申请日：2023-09-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Mari Saji ,  Akira Fujihara

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5° to about 60° within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

公开(公告)号：US20240421225A1

公开(公告)日：2024-12-19

申请号：US18335641

申请日：2023-06-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Anil Kumar ,  Sinan Goktepeli ,  Hiroshi Yamada ,  Akira Fujihara ,  Tsunekazu Saimei ,  Kazuhiko Shibata

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.