公开(公告)号：US20250056875A1

公开(公告)日：2025-02-13

申请号：US18366887

申请日：2023-08-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Simon Edward Willard

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Integrated circuit structures that significantly reduce the resistance associated with the body contact region and substrate region contact of a field-effect transistor (FET) compared to conventional designs. Embodiments include a FET having a body contact region, and optionally a substrate region contact, that includes germanium (Ge) alone or as an alloy with silicon (SiGe) and/or as a layered combination with silicon (e.g., a layer of Ge on a layer of Si). A first method includes fabricating a body contact region of a field-effect transistor by fabricating the field-effect transistor with an Si body contact region, and diffusing or implanting Ge within the Si. A second method includes fabricating a body contact region of a field-effect transistor by fabricating the field-effect transistor with an Si body contact region, etching away at least part of the Si body contact region to form a well, and depositing Ge within the well.

公开(公告)号：US20250098286A1

公开(公告)日：2025-03-20

申请号：US18468556

申请日：2023-09-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Mari Saji ,  Akira Fujihara

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5° to about 60° within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

公开(公告)号：US20240421225A1

公开(公告)日：2024-12-19

申请号：US18335641

申请日：2023-06-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Anil Kumar ,  Sinan Goktepeli ,  Hiroshi Yamada ,  Akira Fujihara ,  Tsunekazu Saimei ,  Kazuhiko Shibata

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.

公开(公告)号：US20240313081A1

公开(公告)日：2024-09-19

申请号：US18185285

申请日：2023-03-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Simon Edward Willard

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/7838

Abstract: FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage VTE of the edge FETs is increased to a level that is at least equal to the threshold voltage VTC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-κ) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-κ material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high-κ material; and a P-type work function material overlaying and in contact with at least one edge portion of the high-κ material.