公开(公告)号：US20240421225A1

公开(公告)日：2024-12-19

申请号：US18335641

申请日：2023-06-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Anil Kumar ,  Sinan Goktepeli ,  Hiroshi Yamada ,  Akira Fujihara ,  Tsunekazu Saimei ,  Kazuhiko Shibata

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.

公开(公告)号：US20250063780A1

公开(公告)日：2025-02-20

申请号：US18451554

申请日：2023-08-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Sinan Goktepeli ,  Kouassi Sebastien Kouassi

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Nano-pillar field-effect transistor (FET) structure that include one or more of the following characteristics: vertical device structure and vertical current flow; vertically displaced source and drain regions; different nanowire/nanosheet geometries and dimensions for different nano-pillar embodiments; and/or body contacts made through wide nano-pillar structures. In addition, by utilizing layer transfer techniques, direct access to drain contacts of a nano-pillar FET structure is available, which enables a significant improvement in transistor performance (e.g., lower RON resistance, faster switching speed). An additional advantage of the novel nano-pillar FET structures is that available top and bottom contacts may be used in various 3-D integrated circuit structures, such as by using layer transfer and/or hybrid bonding.

公开(公告)号：US20250062157A1

公开(公告)日：2025-02-20

申请号：US18451542

申请日：2023-08-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kouassi Sebastien Kouassi ,  Sinan Goktepeli

IPC: H01L21/762 ,  H01L27/092

Abstract: Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (π-Semi) isolation structures such as shallow trench isolation (STI) and/or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form π-Semi isolation structures; in essence, the in situ semiconductor is restructured to π-Semi. The characteristics of π-Semi, particularly mesoporous π-Semi and microporous π-Semi, include good electrical insulation as well as hole trapping capability. Accordingly, π-Semi used for STI and/or DTI structures provides excellent electrical isolation. A first embodiment comprises a “pre-FET” π-Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET). A second embodiment comprises a “post-FET” π-Semi isolation structure, fabricated after formation of gate, drain, and source structures or regions of a FET.