公开(公告)号：US20240413243A1

公开(公告)日：2024-12-12

申请号：US18752009

申请日：2024-06-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Simon Edward Willard ,  Alain Duvallet

IPC: H01L29/78 ,  H01L21/74 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

公开(公告)号：US20250072062A1

公开(公告)日：2025-02-27

申请号：US18891861

申请日：2024-09-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Simon Edward Willard ,  Alain Duvallet

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ΦMF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ΦMF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

公开(公告)号：US12100734B2

公开(公告)日：2024-09-24

申请号：US17961372

申请日：2022-10-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Simon Edward Willard ,  Alain Duvallet

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/76202 ,  H01L29/0649 ,  H01L29/1041 ,  H01L29/36 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/78

Abstract: FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function ΦMF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function ΦMF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

公开(公告)号：US12113069B2

公开(公告)日：2024-10-08

申请号：US17901189

申请日：2022-09-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Richard James Dowling ,  Hiroshi Yamada ,  Alain Duvallet ,  Ronald Eugene Reedy

IPC: H01L21/00 ,  H01L21/48 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/373 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/4882 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/3735 ,  H01L27/092

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

公开(公告)号：US12062669B2

公开(公告)日：2024-08-13

申请号：US18313826

申请日：2023-05-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Hiroshi Yamada ,  Alain Duvallet

IPC: H01L27/13 ,  H01L21/762 ,  H01L21/84 ,  H01L49/02

CPC classification number: H01L27/13 ,  H01L21/76251 ,  H01L21/84 ,  H01L28/60

Abstract: FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate. Couplings to the resulting capacitor structures include only external connections, only internal connections, or both internal and external connections

公开(公告)号：US12027623B2

公开(公告)日：2024-07-02

申请号：US17167992

申请日：2021-02-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Simon Edward Willard ,  Alain Duvallet

IPC: H01L29/78 ,  H01L21/74 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/66484 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/78606 ,  H01L29/78624 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/4238

Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.