公开(公告)号：US20240413036A1

公开(公告)日：2024-12-12

申请号：US18810032

申请日：2024-08-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Hisatoshi KAWABATA ,  Akira FUJIHARA ,  Hiroshi YAMADA

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/31 ,  H01L23/488

Abstract: A device layer is on a first surface which is one surface of a first insulating layer. The device layer includes a transistor including source regions and drain regions, a source contact electrode connected to a source contact region on surfaces of the source regions, a drain contact electrode connected to a drain contact region on surfaces of the drain regions, wires, and vias. An insulating member is bonded to a second surface of the first insulating layer opposite to the first surface. A conical surface whose apex is located on the second surface, whose central axis is a straight line perpendicular to the second surface, and whose generatrix is a half-line extending toward the insulating member at an angle of 45° with respect to the central axis is defined as a criterion conical surface.

公开(公告)号：US20240413083A1

公开(公告)日：2024-12-12

申请号：US18812864

申请日：2024-08-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Hiroshi YAMADA ,  Akira FUJIHARA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786

Abstract: A first insulating layer containing a silicon oxide is disposed on a surface of an insulating member. A transistor is disposed over a part of an area of a first insulating layer. A second insulating layer covers the first insulating layer and the transistor. A first wiring is disposed on the second insulating layer. A through-hole extends through the second insulating layer and the first insulating layer from a lower surface of the first wiring to the insulating member. At least a part of an outer edge of the through-hole overlaps the first wiring in a plan view. The first wiring includes a lower layer that is in contact with the second insulating layer, and the lower layer is formed from Ta, W, a Ta compound, or a W compound.

公开(公告)号：US20250087552A1

公开(公告)日：2025-03-13

申请号：US18963083

申请日：2024-11-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari SAJI ,  Atsushi KUROKAWA ,  Hiroshi YAMADA

IPC: H01L23/373 ,  H01L23/00 ,  H01L27/12

Abstract: At least one of transistors is in a device layer. A plurality of bumps are on one surface of the device layer. An insulating layer is on a surface of the device layer opposite to the surface having the plurality of bumps. The heat transfer layer is in contact with a surface of the insulating layer opposite to a surface on which the device layer is disposed. The heat transfer layer is formed of an insulating material having a thermal conductivity higher than a thermal conductivity of the insulating layer. When the device layer is viewed in plan view, one first transistor of the transistors includes a non-overlapping portion which is a portion not overlapping with the plurality of bumps, and the heat transfer layer is continuous from a portion overlapping with the non-overlapping portion to a portion overlapping with at least one of the plurality of bumps.