公开(公告)号：US20210035922A1

公开(公告)日：2021-02-04

申请号：US16943243

申请日：2020-07-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki TOKUYA ,  Masahiro SHIBATA ,  Akihiko OZAKI ,  Satoshi GOTO ,  Fumio HARIMA ,  Atsushi KUROKAWA

IPC: H01L23/00 ,  H01L29/737 ,  H01L27/082 ,  H01L23/498 ,  H01L23/66

Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

公开(公告)号：US20200119171A1

公开(公告)日：2020-04-16

申请号：US16710957

申请日：2019-12-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Atsushi KUROKAWA

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36 ,  H01L29/08 ,  H01L29/06

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

公开(公告)号：US20190267479A1

公开(公告)日：2019-08-29

申请号：US16268557

申请日：2019-02-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Yuichi SANO

IPC: H01L29/737 ,  H01L23/00 ,  H01L27/082 ,  H01L25/18 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L23/528 ,  H01L29/205

Abstract: A semiconductor device includes a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and an emitter electrode, the bipolar transistor including a collector layer, a base layer, and an emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the emitter electrode being in contact with the emitter layer; a protective layer disposed on one surface of the semiconductor element; an emitter redistribution layer electrically connected to the emitter electrode via a contact hole in the protective layer; and a stress-relieving layer disposed between the emitter redistribution layer and the emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.

公开(公告)号：US20190172773A1

公开(公告)日：2019-06-06

申请号：US16210135

申请日：2018-12-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Masayuki AOIKE ,  Takayuki TSUTSUI

IPC: H01L23/49 ,  H01L23/532 ,  H01L23/29 ,  H01L23/14

Abstract: A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the wiring. A cavity entirely overlapping with the wiring as viewed from above is formed in the insulating film. A metal member electrically connected to the wiring via the cavity is disposed on the insulating film. The centroid of the cavity is displaced from that of the operating region of the corresponding unit transistor in the first direction. When the cavity having a centroid the closest to the operating region of a unit transistor is defined as the closest proximity cavity, the amount of deviation of the centroid of the closest proximity cavity from that of the operating region of the corresponding unit transistor in the first direction becomes greater from the center to the ends of the arrangement direction of the unit transistors.

公开(公告)号：US20190067460A1

公开(公告)日：2019-02-28

申请号：US16171088

申请日：2018-10-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/737 ,  H01L29/12 ,  H01L29/66 ,  H01L29/36 ,  H01L29/08 ,  H01L29/205 ,  H01L29/10

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm−3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm−3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm−2), and an n-type GaAs layer Si concentration: about 5×1015 cm−3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm−2.

公开(公告)号：US20180247895A1

公开(公告)日：2018-08-30

申请号：US15903908

申请日：2018-02-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuichi SANO ,  Atsushi KUROKAWA ,  Kazuya KOBAYASHI

IPC: H01L23/532 ,  H01L23/485

CPC classification number: H01L23/53252 ,  H01L23/485

Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.

公开(公告)号：US20250087552A1

公开(公告)日：2025-03-13

申请号：US18963083

申请日：2024-11-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari SAJI ,  Atsushi KUROKAWA ,  Hiroshi YAMADA

IPC: H01L23/373 ,  H01L23/00 ,  H01L27/12

Abstract: At least one of transistors is in a device layer. A plurality of bumps are on one surface of the device layer. An insulating layer is on a surface of the device layer opposite to the surface having the plurality of bumps. The heat transfer layer is in contact with a surface of the insulating layer opposite to a surface on which the device layer is disposed. The heat transfer layer is formed of an insulating material having a thermal conductivity higher than a thermal conductivity of the insulating layer. When the device layer is viewed in plan view, one first transistor of the transistors includes a non-overlapping portion which is a portion not overlapping with the plurality of bumps, and the heat transfer layer is continuous from a portion overlapping with the non-overlapping portion to a portion overlapping with at least one of the plurality of bumps.

公开(公告)号：US20200168726A1

公开(公告)日：2020-05-28

申请号：US16774917

申请日：2020-01-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/24 ,  H01L29/417

Abstract: A semiconductor device includes an HBT; emitter wiring which is connected to an emitter electrode of the HBT and covers the HBT; a passivation film having an opening on the HBT in plan view; a UBM layer which is connected to the emitter wiring through the opening and made of a refractory metal with a thickness of 300 nm or more; and a pillar bump which is arranged on the UBM layer and includes a metal post and a solder layer. The UBM layer serves as a stress relaxation layer, thereby relaxing stress on the HBT due to a difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump.

公开(公告)号：US20200161226A1

公开(公告)日：2020-05-21

申请号：US16749904

申请日：2020-01-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Kazuya KOBAYASHI ,  Yuichi SANO

IPC: H01L23/495 ,  H01L23/00

Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.

公开(公告)号：US20150349100A1

公开(公告)日：2015-12-03

申请号：US14821214

申请日：2015-08-07

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/732

CPC classification number: H01L29/7325 ,  H01L29/0821 ,  H01L29/152 ,  H01L29/20 ,  H01L29/7371

Abstract: P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance.

Abstract translation: 各自插入相应的一对n型第一半导体层之间的P型第二半导体层降低了整个集电极层中的表观掺杂浓度，而不降低第一半导体层中的掺杂浓度。 这提高了电容特性的线性，并且能够实现足够的批量生产率。 将相应的第一半导体层之间的每一个第二半导体层插入整个集电极层上的平均载流子浓度，这允许在集电极层内形成宽的耗尽层，结果减少了基极集电极 电容。