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公开(公告)号：US20170345565A1
公开(公告)日：2017-11-30
申请号：US15607763
申请日：2017-05-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazunori USUI
Abstract: In a planar view of a ceramic capacitor that has low ESL and is embeddable into a substrate, lengths of first and second external electrodes are L1, lengths from portions of the first and second external electrodes farthest from a capacitor main body to portions closer to the capacitor main body by about 40% of a thickness of the first or second external electrode in a laminating direction are L2, a ratio L2/L1 is about 80% or more and about 90% or less. In the planar view, a length of a third external electrode is L3, a length from a portion of the third external electrode farthest from the capacitor main body to a portion closer to the capacitor main body by about 40% of a thickness of the third external electrode in the laminating direction is L4, a ratio L4/L3 is about 80% or more.
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Patent Agency Ranking
公开(公告)号：US20250054704A1
公开(公告)日：2025-02-13
申请号：US18932730
申请日：2024-10-31
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazunori USUI , Takashi SAWADA
Abstract: A multilayer ceramic electronic component includes a multilayer body with laminated ceramic layers and internal electrode layers, a first and second main surface opposing each other in a lamination direction, a first and second side surface opposing each other in a width direction, a first and second end surface opposing each other in a length direction, and external electrodes. The internal electrode layers include first and second internal electrode layers alternately laminated with the ceramic layers and exposed to the first and second end surfaces and first and second side surfaces. Each of the first and second external electrodes includes a dense region, and where an area ratio of a conductive component is high and a sparse region where an area ratio of the conductive component is lower than the dense region, and the dense region is located closer to a multilayer body side than the sparse region.
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公开(公告)号：US20250062070A1
公开(公告)日：2025-02-20
申请号：US18937286
申请日：2024-11-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazunori USUI , Tatsunori YASUDA
Abstract: A multilayer ceramic capacitor include a multilayer body including internal electrode layers including first and second internal electrode layers facing each other and separated from each other, and a dielectric layer between the first and second internal electrode layers and including a ceramic material, and an outer electrode selectively connected to the first and second internal electrode layers. Each of the first and second internal electrode layers includes a rare earth oxide distributed along at least one of a pair of interfaces with the dielectric layer.
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公开(公告)号：US20250054703A1
公开(公告)日：2025-02-13
申请号：US18931158
申请日：2024-10-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takashi SAWADA , Kazunori USUI
Abstract: A through-type multilayer ceramic capacitor includes a multilayer body including laminated dielectric layers, inner electrode layers laminated on the dielectric layers, first and second inner electrode layer, a first outer electrode on a first end surface of the multilayer body and connected to the first inner electrode layer, a second outer electrode on a second end surface of the multilayer body and connected to the first inner electrode layer, a third outer electrode on a first side surface of the multilayer body and connected to the second inner electrode layer, and a fourth outer electrode on a second side surface of the multilayer body and connected to the second inner electrode layer. The first outer electrode includes a first plating layer and a first charging electrode, and the second outer electrode includes a second plating layer and a second charging electrode.
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公开(公告)号：US20250054694A1
公开(公告)日：2025-02-13
申请号：US18932732
申请日：2024-10-31
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazunori USUI , Takashi SAWADA
Abstract: A multilayer ceramic electronic component includes a multilayer body including laminated ceramic layers and internal electrode layers. The internal electrode layers include a first internal electrode layer laminated alternately with the ceramic layers and exposed at a first and second end and a second internal electrode layer laminated alternately with the ceramic layers and exposed at a first and second side surface, the multilayer ceramic electronic component further includes a dummy electrode spaced apart from the first and second internal electrode layers and exposed at one of the first and second end surfaces and the first and second side surfaces. A line coverage of a conductive component is smaller than about 50% in a region separated from an exposed portion of the dummy electrode toward a center of the multilayer body by about 50% or more.
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公开(公告)号：US20170345563A1
公开(公告)日：2017-11-30
申请号：US15608149
申请日：2017-05-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazunori USUI
CPC classification number: H01G4/005 , C23C14/34 , H01G4/012 , H01G4/12 , H01G4/1209 , H01G4/232 , H01G4/30 , H01G4/302 , H01G4/306
Abstract: A ceramic capacitor which is low in ESL and suitable for being built into a substrate has a dimension in a length direction of a lowermost surface of a third external electrode which is in contact with a capacitor main body denoted by e1 and a dimension in the length direction of the uppermost surface of the third external electrode denoted by e2, and a relationship of e1
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