-
公开(公告)号：US20240071691A1
公开(公告)日：2024-02-29
申请号：US18502440
申请日：2023-11-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takeshi KAGAWA , Masaki TSUKIDA
Abstract: A capacitor that includes: a substrate having a first principal surface and a second principal surface opposed to each other in a thickness direction, wherein the first principal surfaces includes a step in a plan view from the thickness direction; an insulating film on the first principal surface of the substrate; a first electrode layer on the insulating film and positioned within a boundary defined by the step in the plan view; a dielectric film on the first electrode layer; a second electrode layer on the dielectric film; a moisture-resistant film on the dielectric film and the second electrode layer; a protective layer on the moisture-resistant film; and an outer electrode penetrating through the protective layer.
-
Patent Agency Ranking
公开(公告)号：US20160155569A1
公开(公告)日：2016-06-02
申请号：US14943771
申请日：2015-11-17
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masaki TSUKIDA , Hiroshi MASAI
Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
Abstract translation: 一种层叠电容器的制造方法包括：从层叠方向观察时，交替层叠电介质层和包含小于50的第一布置的导体层和与第一布置不同的第二布置，以形成层压体，其中至少一对 在第一或第二布置中包括彼此相邻的导电体层，介于第一或第二布置之间，压制层压体以沿与层叠方向垂直或基本垂直的方向拉伸导体层，按压层压体以弯曲导体层 并且在层叠表面上形成第一和第二外部电极，使得第一外部电极连接到包括在第一布置中的导体层，第二外部电极连接到包括在第二布置中的导体层。
-
公开(公告)号：US20190027310A1
公开(公告)日：2019-01-24
申请号：US16137579
申请日：2018-09-21
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masaki TSUKIDA , Hiroshi MASAI
Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
-
公开(公告)号：US20180053600A1
公开(公告)日：2018-02-22
申请号：US15802642
申请日：2017-11-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masaki TSUKIDA , Hiroshi MASAI
Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
-
公开(公告)号：US20180075969A1
公开(公告)日：2018-03-15
申请号：US15802648
申请日：2017-11-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masaki TSUKIDA , Hiroshi MASAI
Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
-
公开(公告)号：US20160247632A1
公开(公告)日：2016-08-25
申请号：US15014164
申请日：2016-02-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masaki TSUKIDA , Hiroshi MASAI
CPC classification number: H01G4/232 , H01G4/005 , H01G4/0085 , H01G4/012 , H01G4/30
Abstract: A multilayer capacitor includes a multilayer body with sides each about 0.3 mm or smaller when viewed from a stacking direction of the multilayer body, and first and second outer electrodes disposed on a surface of the multilayer body. An outermost one of the conductive layers is bent to be convex in the stacking direction and includes penetrating portions extending in the stacking direction. In a cross section perpendicular or substantially perpendicular to a lengthwise direction of the multilayer body, assuming the bent conductive layer is equally divided into four regions named region A, region B, region C, and region D arranged in the order named in a widthwise direction of the multilayer body, a sum of minimum diameters of the penetrating portions is larger in the region A than in the region B and larger in the region D than in the region C.
Abstract translation: 多层电容器包括从多层体的堆叠方向观察时侧面为约0.3mm以下的侧面的多层体，以及设置在多层体的表面的第一外部电极和第二外部电极。 导电层中的最外面的一个导体层在层叠方向上被弯曲成凸起，并且包括沿堆叠方向延伸的穿透部。 在垂直于或基本上垂直于多层体的纵向方向的截面中，假设弯曲的导电层被等分成四个区域，区域A，区域B，区域C和区域D按照宽度方向 在区域A中的穿透部的最小直径的和比区域B中的最小直径的和大，在区域D中比在区域C中大。
-
-
-
-
-
Search Results
6
records
(took 0.013 seconds)
