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    Memory system including a power divider on a multi module memory bus
    1.
    发明授权
    Memory system including a power divider on a multi module memory bus 有权
    存储系统包括多模块存储器总线上的功率分配器

    公开(公告)号：US07646212B2

    公开(公告)日：2010-01-12

    申请号：US11668397

    申请日：2007-01-29

    申请人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

    发明人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

    IPC分类号： H03K19/003

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C5/14

    摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

    摘要翻译： 存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。 传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。 功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。 第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。 因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。

    MEMORY SYSTEM INCLUDING A POWER DIVIDER ON A MULTI MODULE MEMORY BUS
    2.
    发明申请
    MEMORY SYSTEM INCLUDING A POWER DIVIDER ON A MULTI MODULE MEMORY BUS 有权
    在多模块存储器总线上包括功率分配器的存储器系统

    公开(公告)号：US20070194968A1

    公开(公告)日：2007-08-23

    申请号：US11668397

    申请日：2007-01-29

    申请人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

    发明人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

    IPC分类号： H03M1/78

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C5/14

    摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

    摘要翻译： 存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。 传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。 功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。 第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。 因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。

    Address Driving Circuit and Plasma Display Device Having the Same
    4.
    发明申请
    Address Driving Circuit and Plasma Display Device Having the Same 失效
    地址驱动电路和等离子体显示设备具有相同的功能

    公开(公告)号：US20100164932A1

    公开(公告)日：2010-07-01

    申请号：US12634227

    申请日：2009-12-09

    申请人： Joung-Ho Kim ,  Hyo-Sang Youn ,  Tae-Ho Kwon

    发明人： Joung-Ho Kim ,  Hyo-Sang Youn ,  Tae-Ho Kwon

    IPC分类号： G09G5/00 ,  G09G3/28 ,  H03B1/00

    CPC分类号： G09G3/293 ,  G09G3/296 ,  G09G2330/06

    摘要： An address driving circuit includes a driving device unit and an energy recovery circuit. The driving device unit drives an address electrode to an address voltage or a reference voltage in response to driving control signals during an address period. The energy recovery circuit recovers a voltage charged to the address electrode in response to switching control signals such that a voltage of the address electrode transitions to the address voltage or the reference voltage via at least two intermediate voltages including first and second intermediate voltages during the address period.

    摘要翻译： 地址驱动电路包括驱动装置单元和能量恢复电路。 驱动装置单元响应于在寻址周期期间的驱动控制信号将寻址电极驱动到寻址电压或参考电压。 能量回收电路响应于切换控制信号而恢复向地址电极充电的电压，使得地址电极的电压在地址期间经由包括第一和第二中间电压的至少两个中间电压而转变到寻址电压或参考电压 期。

    Semiconductor integrated circuit devices
    5.
    发明申请
    Semiconductor integrated circuit devices 有权
    半导体集成电路器件

    公开(公告)号：US20090267148A1

    公开(公告)日：2009-10-29

    申请号：US12382596

    申请日：2009-03-19

    申请人： Yong-Don Kim ,  Yong-Chan Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Eung-Kyu Lee ,  Jong-Wook Lim

    发明人： Yong-Don Kim ,  Yong-Chan Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Eung-Kyu Lee ,  Jong-Wook Lim

    IPC分类号： H01L27/088 ,  H01L29/78

    CPC分类号： H01L27/092 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

    摘要： A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.

    摘要翻译： 半导体集成电路器件可以包括：衬底，其包括限定在衬底上的高电压器件区域和低电压器件区域; 形成在所述高电压器件区域的至少一部分中并耦合到第一电压的第一掩埋杂质层; 第二掩埋杂质层，形成在所述低电压器件区域的至少一部分中并耦合到小于所述第一电压的第二电压; 以及在低电压器件区域中的第二掩埋杂质层上良好地形成，并且耦合到小于第二电压的第三电压。

    High power address driver and display device employing the same
    6.
    发明申请
    High power address driver and display device employing the same 审中-公开
    大功率地址驱动器和使用该驱动器的显示设备

    公开(公告)号：US20090009434A1

    公开(公告)日：2009-01-08

    申请号：US12213936

    申请日：2008-06-26

    申请人： Yong-Don Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Yong-Chan Kim ,  Sun-Hak Lee

    发明人： Yong-Don Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Yong-Chan Kim ,  Sun-Hak Lee

    IPC分类号： G09G3/28 ,  H03K19/094 ,  G09G5/00

    CPC分类号： G09G3/2965 ,  G09G3/293 ,  G09G3/296 ,  G09G2330/021 ,  G09G2330/028

    摘要： An address driver includes an energy recovery circuit and an output stage connected to the energy recovery circuit. The output stage is connected to the energy recovery circuit and is formed of a pull-up MOS transistor and a pull-down MOS transistor in series. A source terminal of the pull-up MOS transistor is connected to the energy recovery circuit, and a bulk terminal of the pull-up MOS transistor is connected to a node providing a reverse bias between the source terminal and the bulk terminal of the pull-up MOS transistor. A display device employing the address driver is also provided.

    摘要翻译： 地址驱动器包括能量恢复电路和连接到能量恢复电路的输出级。 输出级与能量恢复电路相连，由串联的上拉MOS晶体管和下拉式MOS晶体管构成。 上拉MOS晶体管的源极端子连接到能量恢复电路，并且上拉MOS晶体管的体式端子连接到在源极端子和拉出型MOS晶体管的体式端子之间提供反向偏置的节点， up MOS晶体管。 还提供了采用地址驱动器的显示装置。

    Address driving circuit and plasma display device having the same
    8.
    发明授权
    Address driving circuit and plasma display device having the same 失效
    地址驱动电路和等离子体显示装置

    公开(公告)号：US08368682B2

    公开(公告)日：2013-02-05

    申请号：US12634227

    申请日：2009-12-09

    申请人： Joung-Ho Kim ,  Hyo-Sang Youn ,  Tae-Ho Kwon

    发明人： Joung-Ho Kim ,  Hyo-Sang Youn ,  Tae-Ho Kwon

    IPC分类号： G09G5/00

    CPC分类号： G09G3/293 ,  G09G3/296 ,  G09G2330/06

    摘要： An address driving circuit includes a driving device unit and an energy recovery circuit. The driving device unit drives an address electrode to an address voltage or a reference voltage in response to driving control signals during an address period. The energy recovery circuit recovers a voltage charged to the address electrode in response to switching control signals such that a voltage of the address electrode transitions to the address voltage or the reference voltage via at least two intermediate voltages including first and second intermediate voltages during the address period.

    摘要翻译： 地址驱动电路包括驱动装置单元和能量恢复电路。 驱动装置单元响应于在寻址周期期间的驱动控制信号将寻址电极驱动到寻址电压或参考电压。 能量回收电路响应于切换控制信号而恢复向地址电极充电的电压，使得地址电极的电压在地址期间经由包括第一和第二中间电压的至少两个中间电压而转变到寻址电压或参考电压 期。

    Semiconductor integrated circuit devices
    9.
    发明授权
    Semiconductor integrated circuit devices 有权
    半导体集成电路器件

    公开(公告)号：US07960785B2

    公开(公告)日：2011-06-14

    申请号：US12382596

    申请日：2009-03-19

    申请人： Yong-Don Kim ,  Yong-Chan Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Eung-Kyu Lee ,  Jong-Wook Lim

    发明人： Yong-Don Kim ,  Yong-Chan Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Eung-Kyu Lee ,  Jong-Wook Lim

    IPC分类号： H01L27/088

    CPC分类号： H01L27/092 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

    摘要： A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.

    摘要翻译： 半导体集成电路器件可以包括：衬底，其包括限定在衬底上的高电压器件区域和低电压器件区域; 形成在所述高电压器件区域的至少一部分中并耦合到第一电压的第一掩埋杂质层; 第二掩埋杂质层，形成在所述低电压器件区域的至少一部分中并耦合到小于所述第一电压的第二电压; 以及在低电压器件区域中的第二掩埋杂质层上良好地形成，并且耦合到小于第二电压的第三电压。