公开(公告)号：US20070145467A1

公开(公告)日：2007-06-28

申请号：US11538239

申请日：2006-10-03

申请人： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

发明人： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L29/66825

摘要： An EEPROM includes a semiconductor substrate and a device isolation region defining first, second and third active regions in the semiconductor substrate. The EEPROM also includes at least one first insulation region in at least one first trench in the first active region. A floating gate insulation layer is disposed on the at least one first insulation region and the first, second and third active regions and a floating gate conduction layer is disposed on the floating gate insulation layer. Impurity-containing regions may be disposed in each of the first, second and third active regions at respective sides of the floating gate conduction layer. The floating gate insulation layer may include at least one thinned portion proximate the at least one first insulation region, which may aid Fowler-Nordheim tunneling at this site.

摘要翻译： EEPROM包括半导体衬底和限定半导体衬底中的第一，第二和第三有源区的器件隔离区。 EEPROM还包括在第一有源区域中的至少一个第一沟槽中的至少一个第一绝缘区域。 浮置栅极绝缘层设置在至少一个第一绝缘区域和第一，第二和第三有源区域上，并且浮置栅极导电层设置在浮置栅极绝缘层上。 含杂质的区域可以布置在浮置栅极导电层的相应侧的第一，第二和第三有源区域的每一个中。 浮栅绝缘层可以包括靠近至少一个第一绝缘区域的至少一个变薄部分，这可以有助于在该部位的Fowler-Nordheim隧道。

公开(公告)号：US20070148851A1

公开(公告)日：2007-06-28

申请号：US11608529

申请日：2006-12-08

申请人： Myung-hee Kim ,  Geun-sook Park ,  Sang-bae Yi ,  Ho-ik Hwang ,  Hye-young Park

发明人： Myung-hee Kim ,  Geun-sook Park ,  Sang-bae Yi ,  Ho-ik Hwang ,  Hye-young Park

IPC分类号： H01L21/8238

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A method of programming an EEPROM including a first active region, a second active region and a third active region located separately in a semiconductor substrate, a common floating gate above and intersecting the active regions, first impurity regions located at both sides of the common floating gate in the first active region, second impurity regions located at both sides of the common floating gate in the second active regions and third impurity region, located at both sides of the common floating gate in the third active region. The method includes: applying a programming voltage to the first impurity regions in the first active region and the third impurity regions in the third active region; and applying a ground voltage to the second impurity regions in the second active region.

摘要翻译： 一种编程EEPROM的方法，包括分别位于半导体衬底中的第一有源区，第二有源区和第三有源区，位于有源区之上并与有源区相交的公共浮栅，位于公共浮置的两侧的第一杂质区 位于第一有源区中的栅极，位于第二有源区域中的公共浮置栅极两侧的第二杂质区域和位于第三有源区域中的公共浮置栅极两侧的第三杂质区域。 该方法包括：对第一有源区中的第一杂质区和第三有源区中的第三杂质区施加编程电压; 以及对第二有源区中的第二杂质区施加接地电压。

公开(公告)号：US07705409B2

公开(公告)日：2010-04-27

申请号：US12014244

申请日：2008-01-15

申请人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

发明人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66568

摘要： Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

摘要翻译： 本发明的一些实施例提供了包括半导体衬底和限定半导体衬底中的有源区的器件隔离膜的高压晶体管。 栅电极沿着有源区的中心部分延伸，同时保持半导体衬底上的预定宽度。 第二阱形成在半导体衬底中的栅电极的两侧，并且部分地延伸到器件隔离膜的底表面。 半导体衬底中的有源区域包括设置在栅电极下方的第一有源区，以及分离器件隔离膜和由第一有源区和器件隔离膜限定的第二有源区。 还提供制造高压晶体管的方法。

公开(公告)号：US20080185664A1

公开(公告)日：2008-08-07

申请号：US12014244

申请日：2008-01-15

申请人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

发明人： Oh-kyum Kwon ,  Yong-chan Kim ,  Joon-suk Oh ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66568

摘要： Some embodiments of the present invention provide high voltage transistors including a semiconductor substrate and a device isolation film defining an active region in the semiconductor substrate. A gate electrode extends along a central portion of the active region while maintaining a predetermined width on the semiconductor substrate. A second well is formed on both sides of the gate electrode in the semiconductor substrate, and partially extends to a bottom surface of the device isolation film. The active region in the semiconductor substrate comprises a first active region disposed under the gate electrode, and separating the device isolation film and a second active region defined by the first active region and the device isolation film. Methods of manufacturing high voltage transistors are also provided.

摘要翻译： 本发明的一些实施例提供了包括半导体衬底和限定半导体衬底中的有源区的器件隔离膜的高压晶体管。 栅电极沿着有源区的中心部分延伸，同时保持半导体衬底上的预定宽度。 第二阱形成在半导体衬底中的栅电极的两侧，并且部分地延伸到器件隔离膜的底表面。 半导体衬底中的有源区域包括设置在栅电极下方的第一有源区，以及分离器件隔离膜和由第一有源区和器件隔离膜限定的第二有源区。 还提供制造高压晶体管的方法。