公开(公告)号：US20080293205A1

公开(公告)日：2008-11-27

申请号：US12125224

申请日：2008-05-22

Applicant: Oh-Kyum KWON ,  Bum-Seok KIM ,  Geun-Sook PARK ,  Joon-Suk OH ,  Hye-Young PARK ,  Min-Jun CHOI

Inventor： Oh-Kyum KWON ,  Bum-Seok KIM ,  Geun-Sook PARK ,  Joon-Suk OH ,  Hye-Young PARK ,  Min-Jun CHOI

IPC: H01L21/336 ,  H01L21/44

CPC classification number: H01L29/872 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/66143 ,  H01L29/665

Abstract: A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.

Abstract translation: 形成金属硅化物层的方法包括在基板上依次形成金属层和第一覆盖层，在基板上进行第一热处理以使基板与金属层反应，去除第一封盖层和 未反应的金属层，在衬底上形成第二覆盖层，并在衬底上进行第二热处理，以在衬底上形成金属硅化物层。

公开(公告)号：US20070145467A1

公开(公告)日：2007-06-28

申请号：US11538239

申请日：2006-10-03

Applicant: Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

Inventor： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L29/66825

Abstract: An EEPROM includes a semiconductor substrate and a device isolation region defining first, second and third active regions in the semiconductor substrate. The EEPROM also includes at least one first insulation region in at least one first trench in the first active region. A floating gate insulation layer is disposed on the at least one first insulation region and the first, second and third active regions and a floating gate conduction layer is disposed on the floating gate insulation layer. Impurity-containing regions may be disposed in each of the first, second and third active regions at respective sides of the floating gate conduction layer. The floating gate insulation layer may include at least one thinned portion proximate the at least one first insulation region, which may aid Fowler-Nordheim tunneling at this site.

Abstract translation: EEPROM包括半导体衬底和限定半导体衬底中的第一，第二和第三有源区的器件隔离区。 EEPROM还包括在第一有源区域中的至少一个第一沟槽中的至少一个第一绝缘区域。 浮置栅极绝缘层设置在至少一个第一绝缘区域和第一，第二和第三有源区域上，并且浮置栅极导电层设置在浮置栅极绝缘层上。 含杂质的区域可以布置在浮置栅极导电层的相应侧的第一，第二和第三有源区域的每一个中。 浮栅绝缘层可以包括靠近至少一个第一绝缘区域的至少一个变薄部分，这可以有助于在该部位的Fowler-Nordheim隧道。

公开(公告)号：US20070145459A1

公开(公告)日：2007-06-28

申请号：US11643837

申请日：2006-12-22

Applicant: Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

Inventor： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC: H01L29/76

CPC classification number: H01L27/11558 ,  H01L27/115 ,  H01L27/11521

Abstract: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract translation: 在一个方面，提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US06534370B2

公开(公告)日：2003-03-18

申请号：US09776753

申请日：2001-02-06

Applicant: Geun-Sook Park

Inventor： Geun-Sook Park

IPC: H01L21336

CPC classification number: H01L29/66621 ,  H01L21/0274 ,  H01L21/3081 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7834

Abstract: The present invention is a method for fabricating a semiconductor device having an elevated source/drain scheme which includes the steps of: forming a first photoresist film on a top surface of a semiconductor substrate; forming a second photoresist film on the first photoresist film; forming the second photoresist film; forming a second photoresist film pattern so that a portion corresponding to a field region has a first opening and a region in which a gate electrode is to be formed has a second opening by exposing the second photoresist film to a first light, thereby developing the second photoresist film; forming a first photoresist film pattern so that a portion corresponding to the field region has a third opening by exposing the first photoresist film to a second light, thereby developing the first photoresist film; forming a first trench at the first opening position and a second trench at the second opening position on the semiconductor substrate by etching the semiconductor substrate using the first photoresist film pattern and the second photoresist film pattern as a mask; filling the first trench and the second trench with an oxide film; removing the oxide film in the second trench; forming a gate oxide film on inner walls of the first and second trenches and on the top surface of the semiconductor substrate; forming a gate electrode on a top surface of the second trench by forming a conductive layer on a top surface of the gate oxide film and patterning the gate oxide film; and forming a source junction and a drain junction by implanting impurity ions in the semiconductor substrate at both sides of the gate electrode.

公开(公告)号：US07593261B2

公开(公告)日：2009-09-22

申请号：US11643837

申请日：2006-12-22

Applicant: Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

Inventor： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC: G11C11/03

CPC classification number: H01L27/11558 ,  H01L27/115 ,  H01L27/11521

Abstract: An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract translation: 提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US20070148851A1

公开(公告)日：2007-06-28

申请号：US11608529

申请日：2006-12-08

Applicant: Myung-hee Kim ,  Geun-sook Park ,  Sang-bae Yi ,  Ho-ik Hwang ,  Hye-young Park

Inventor： Myung-hee Kim ,  Geun-sook Park ,  Sang-bae Yi ,  Ho-ik Hwang ,  Hye-young Park

IPC: H01L21/8238

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

Abstract: A method of programming an EEPROM including a first active region, a second active region and a third active region located separately in a semiconductor substrate, a common floating gate above and intersecting the active regions, first impurity regions located at both sides of the common floating gate in the first active region, second impurity regions located at both sides of the common floating gate in the second active regions and third impurity region, located at both sides of the common floating gate in the third active region. The method includes: applying a programming voltage to the first impurity regions in the first active region and the third impurity regions in the third active region; and applying a ground voltage to the second impurity regions in the second active region.

Abstract translation: 一种编程EEPROM的方法，包括分别位于半导体衬底中的第一有源区，第二有源区和第三有源区，位于有源区之上并与有源区相交的公共浮栅，位于公共浮置的两侧的第一杂质区 位于第一有源区中的栅极，位于第二有源区域中的公共浮置栅极两侧的第二杂质区域和位于第三有源区域中的公共浮置栅极两侧的第三杂质区域。 该方法包括：对第一有源区中的第一杂质区和第三有源区中的第三杂质区施加编程电压; 以及对第二有源区中的第二杂质区施加接地电压。

公开(公告)号：US08050091B2

公开(公告)日：2011-11-01

申请号：US12542787

申请日：2009-08-18

Applicant: Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

Inventor： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC: G11C16/04

CPC classification number: H01L27/11558 ,  H01L27/115 ,  H01L27/11521

Abstract: An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract translation: 提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US20090310427A1

公开(公告)日：2009-12-17

申请号：US12542787

申请日：2009-08-18

Applicant: Geun-sook PARK ,  Sang-bae YI ,  Soo-cheol LEE ,  Ho-ik HWANG ,  Tae-jung LEE

Inventor： Geun-sook PARK ,  Sang-bae YI ,  Soo-cheol LEE ,  Ho-ik HWANG ,  Tae-jung LEE

IPC: G11C16/04

CPC classification number: H01L27/11558 ,  H01L27/115 ,  H01L27/11521

Abstract: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

Abstract translation: 在一个方面，提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。