公开(公告)号：US11895829B2

公开(公告)日：2024-02-06

申请号：US17837718

申请日：2022-06-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Pei-Rou Jiang ,  Chao-Wen Lay

IPC分类号： H10B12/00

CPC分类号： H10B12/482

摘要： The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

公开(公告)号：US11882690B2

公开(公告)日：2024-01-23

申请号：US17837052

申请日：2022-06-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Pei-Rou Jiang ,  Chao-Wen Lay

IPC分类号： H10B12/00 ,  H01L21/768

CPC分类号： H10B12/482 ,  H01L21/76852

摘要： The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.