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8 条记录 (耗时 0.013 秒)

    Method of forming a semicondcutor device using carbon containing spacer for a bitline
    2.
    发明授权
    Method of forming a semicondcutor device using carbon containing spacer for a bitline 有权

    公开(公告)号：US11804404B2

    公开(公告)日：2023-10-31

    申请号：US17450833

    申请日：2021-10-14

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chao-Wen Lay

    IPC分类号： H10B12/00 ,  H01L21/768 ,  G11C5/06 ,  H01L23/532 ,  H01L23/528

    CPC分类号： H01L21/76837 ,  G11C5/063 ,  H01L21/76828 ,  H01L23/5283 ,  H01L23/5329 ,  H10B12/482

    摘要： A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.

    Method of manufacturing semiconductor structure having tapered bit line
    4.
    发明授权
    Method of manufacturing semiconductor structure having tapered bit line 有权

    公开(公告)号：US11895829B2

    公开(公告)日：2024-02-06

    申请号：US17837718

    申请日：2022-06-10

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Pei-Rou Jiang ,  Chao-Wen Lay

    IPC分类号： H10B12/00

    CPC分类号： H10B12/482

    摘要： The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

    Semiconductor structure having tapered bit line
    6.
    发明授权
    Semiconductor structure having tapered bit line 有权

    公开(公告)号：US11882690B2

    公开(公告)日：2024-01-23

    申请号：US17837052

    申请日：2022-06-10

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Pei-Rou Jiang ,  Chao-Wen Lay

    IPC分类号： H10B12/00 ,  H01L21/768

    CPC分类号： H10B12/482 ,  H01L21/76852

    摘要： The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.

    Semicondcutor device and manufacturing method thereof
    7.
    发明授权
    Semicondcutor device and manufacturing method thereof 有权

    公开(公告)号：US11462548B1

    公开(公告)日：2022-10-04

    申请号：US17355142

    申请日：2021-06-22

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chao-Wen Lay

    IPC分类号： H01L27/108

    摘要： A semiconductor device includes a semiconductor structure, a first dielectric layer and a plurality of multilayer stacks. The semiconductor structure includes conductive features therein. The first dielectric layer is on the semiconductor structure. The multilayer stacks are arranged on the first dielectric layer. Each of the multilayer stacks comprises a semiconductor layer over the first dielectric layer, a conductive layer over the semiconductor layer and a second dielectric layer over the conductive layer. The second dielectric layer includes a top portion and a bottom portion wider than the top portion.