公开(公告)号：US20040196419A1

公开(公告)日：2004-10-07

申请号：US10831118

申请日：2004-04-26

Applicant: NEC CORPORATION ,  NEC LCD TECHNOLOGIES, LTD

Inventor： Hiroshi Kanou ,  Yuichi Yamaguchi ,  Teruaki Suzuki ,  Hironori Kikkawa

IPC: G02F001/1335

CPC classification number: G02F1/136227 ,  G02F1/133345 ,  G02F1/133553

Abstract: A reflection-type liquid crystal display according to the invention includes two glass substrates, a transparent electrode provided on one glass substrate, an insulator film which is provided on another glass substrate and on which an uneven structure is formed, a reflecting electrode provided on the insulator film, and a liquid crystal layer sandwiched between a side of the transparent electrode and a side of the reflecting electrode. The insulator film includes a first insulating layer in which a large number of depressions isolated as surrounded by protrusions are irregularly arranged and a second insulating layer covering the insulating layer entirely. The protrusions are all connected in a network, so that if some of these protrusions have weaker adherence with an underlying layer, they can be supported by the surrounding protrusions.

公开(公告)号：US20040084672A1

公开(公告)日：2004-05-06

申请号：US10617035

申请日：2003-07-11

Applicant: NEC LCD Technologies, Ltd.

Inventor： Hiroaki Tanaka ,  Hirotaka Yamaguchi ,  Wakahiko Kaneko ,  Michiaki Sakamoto ,  Satoshi Ihida ,  Takasuke Hayase ,  Tae Yoshikawa ,  Hiroshi Kanou

IPC: H01L029/00 ,  H01L021/02

CPC classification number: H01L27/12 ,  G02F1/134363 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another from layer to layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer (102 of FIG. 6) and a TFF area. A drain electrode layer (106 of FIG. 6) is formed by a first passivation film (105 of FIG. 6) via a first passivation film (105 of FIG. 6) formed as an upper layer. In a second passivation film (107 of FIG. 6) formed above it are bored an opening through the first and second passivation films and an opening through the second passivation film. A wiring connection layer is formed by ITO (108 of FIG. 6) provided as an uppermost layer. A storage capacitance unit, comprised of the first and second passivation films sandwiched between the gate electrode and an electrode layer formed as a co-layer with respect to the gate electrode, is provided in the pixel electrode.