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公开(公告)号：US11558064B2
公开(公告)日：2023-01-17
申请号：US17616643
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： Daiguo Xu , Hequan Jiang , Ruzhang Li , Jianan Wang , Guangbing Chen , Yuxin Wang , Dongbing Fu , Liang Li , Yan Wang
摘要： SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.
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公开(公告)号：US11728820B2
公开(公告)日：2023-08-15
申请号：US17279101
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Daiguo Xu , Hequan Jiang , Xueliang Xu , Jian'an Wang , Guangbing Chen , Dongbing Fu , Yuxin Wang , Xiaoquan Yu , Shiliu Xu , Tao Liu
IPC分类号： H03M1/44 , H03M1/12 , H03K3/0233 , H03K19/017 , H03K19/17736
CPC分类号： H03M1/44 , H03K3/0233 , H03K19/01728 , H03K19/1774 , H03M1/125
摘要： The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.
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公开(公告)号：US10778092B2
公开(公告)日：2020-09-15
申请号：US16605804
申请日：2017-09-11
发明人： Rongbin Hu , Yonglu Wang , Zhengping Zhang , Jian'an Wang , Guangbing Chen , Dongbing Fu , Yuxin Wang , Hequan Jiang , Gangyi Hu
摘要： The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
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公开(公告)号：US11848062B2
公开(公告)日：2023-12-19
申请号：US17925320
申请日：2020-09-01
发明人： Yan Wang , Peijian Zhang , Mingyuan Xu , Xian Chen , Feiyu Jiang , Xiyi Liao , Sheng Qiu , Zhengyuan Zhang , Ruzhang Li , Hequan Jiang , Yonghong Dai
摘要： A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.
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公开(公告)号：US12044583B2
公开(公告)日：2024-07-23
申请号：US16636021
申请日：2017-09-11
发明人： Rongbin Hu , Jian'an Wang , Dongbing Fu , Guangbing Chen , Zhengping Zhang , Hequan Jiang , Gangyi Hu
CPC分类号： G01K7/01 , G01K15/005 , G01K2219/00
摘要： A digital temperature sensor circuit is disclosed. The digital temperature sensor circuit includes a proportional to the absolute temperature (PTAT) current source, generating a PTAT current proportional to absolute temperature; a sigma-delta modulation module, including an integrator, an analog-to-digital conversion unit, and a feedback digital-to-analog conversion unit; the integrator converts the PTAT current into temperature voltage; the analog-to-digital conversion unit compares the temperature voltage with a band gap reference voltage to generate a digital modulation signal with a duty ratio proportional to the temperature; the feedback digital-to-analog conversion unit adjusts the voltage input by the analog-to-digital conversion unit and controls the charging and discharging speed of the integrator; a digital filter, quantizing the digital modulation signal into a digital signal, and outputting the digital signal.
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