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公开(公告)号：US11502657B2
公开(公告)日：2022-11-15
申请号：US17040516
申请日：2018-07-25
发明人： Xiaofeng Shen , Xingfa Huang , Liang Li , Xi Chen , Mingyuan Xu , Jian'an Wang , Dongbing Fu , Guangbing Chen
摘要： A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.
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公开(公告)号：US11848062B2
公开(公告)日：2023-12-19
申请号：US17925320
申请日：2020-09-01
发明人： Yan Wang , Peijian Zhang , Mingyuan Xu , Xian Chen , Feiyu Jiang , Xiyi Liao , Sheng Qiu , Zhengyuan Zhang , Ruzhang Li , Hequan Jiang , Yonghong Dai
摘要： A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.
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公开(公告)号：US11323129B2
公开(公告)日：2022-05-03
申请号：US17257315
申请日：2018-12-13
发明人： Jie Pu , Gangyi Hu , Dongbing Fu , Zhengping Zhang , Liang Li , Ting Li , Daiguo Xu , Mingyuan Xu , Xiaofeng Shen , Xianjie Wan , Youhua Wang
摘要： The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
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公开(公告)号：US11290091B2
公开(公告)日：2022-03-29
申请号：US17276829
申请日：2019-08-01
发明人： Xi Chen , Xiaofeng Shen , Xingfa Huang , Liang Li , Mingyuan Xu , Jian'an Wang , Dongbing Fu , Guangbing Chen
IPC分类号： H03K3/356 , H03K5/22 , H03K17/687 , H03K5/00
摘要： The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.
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公开(公告)号：US11353505B2
公开(公告)日：2022-06-07
申请号：US17602993
申请日：2020-01-07
申请人： NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： Mingyuan Xu , Liang Li , Jun Liu , Xiaofeng Shen , Jianan Wang , Dongbing Fu , Guangbing Chen , Xingfa Huang , Xi Chen
IPC分类号： G01R31/317 , H03K19/0948
摘要： The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK−) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK−) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.
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公开(公告)号：US11251788B2
公开(公告)日：2022-02-15
申请号：US16082066
申请日：2017-07-21
发明人： Xi Chen , Liang Li , Guangbing Chen , Yuxin Wang , Dongbing Fu , Xingfa Huang , Mingyuan Xu , Xiaofeng Shen
摘要： A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.
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公开(公告)号：US20210211122A1
公开(公告)日：2021-07-08
申请号：US16082066
申请日：2017-07-21
发明人： Xi Chen , Liang Li , Guangbing Chen , Yuxin Wang , Dongbing Fu , Xingfa Huang , Mingyuan Xu , Xiaofeng Shen
摘要： A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.
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