公开(公告)号：US20250156321A1

公开(公告)日：2025-05-15

申请号：US18506007

申请日：2023-11-09

Applicant: NVIDIA CORPORATION

Inventor： Ashutosh PANDEY ,  Steven E. MOLNAR ,  Mirko ANDJIC ,  Amit PABALKAR ,  Harold W. CAIN, III ,  Prabal Sharma

IPC: G06F12/0802

Abstract: Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

公开(公告)号：US20250156326A1

公开(公告)日：2025-05-15

申请号：US18505952

申请日：2023-11-09

Applicant: NVIDIA CORPORATION

Inventor： Ashutosh PANDEY ,  Steven E. MOLNAR ,  Mirko ANDJIC ,  Amit PABALKAR ,  Harold W. CAIN, III ,  Prabal SHARMA

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/128

Abstract: Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

公开(公告)号：US20200327010A1

公开(公告)日：2020-10-15

申请号：US16384614

申请日：2019-04-15

Applicant: NVIDIA CORPORATION

Inventor： Ashutosh PANDEY ,  Jay GUPTA ,  Kaushal AGARWAL ,  Justin BENNETT ,  Srinivas Santosh Kumar MADUGULA

IPC: G06F11/10 ,  G06F12/06 ,  G06F12/0882 ,  G06F9/46 ,  G06F9/48 ,  G06F13/40

Abstract: Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.