公开(公告)号：US20150301761A1

公开(公告)日：2015-10-22

申请号：US14544468

申请日：2015-01-08

Applicant: NVIDIA Corporation

Inventor： Franciscus SIJSTERMANS ,  Steven MOLNAR ,  Gilberto CONTRERAS ,  Jay HUANG ,  Jay GUPTA ,  Michael WASSERMAN ,  James DEMING

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0623 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/109 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1458 ,  G06F21/60 ,  G06F2212/1052 ,  G06F2212/152

Abstract: Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

Abstract translation: 所要求保护的主题的实施例提供用于在动态分配的存储器区域中保护数据的系统和方法。 该方法可以包括接收读取请求，其中读取请求包括与存储器相关联的虚拟地址并且确定与虚拟地址相关联的物理地址。 还包括确定与虚拟地址相关联的物理地址是否被读取保护并且确定读取请求是否来自允许访问读取保护的存储器的组件。 读取受保护的内存以每页为基础动态分配。 该方法还包括响应于确定读取请求是针对读取保护的物理地址并且确定该组件被允许访问读取保护的存储器，从存储器中的物理地址发送数据。

公开(公告)号：US20200327010A1

公开(公告)日：2020-10-15

申请号：US16384614

申请日：2019-04-15

Applicant: NVIDIA CORPORATION

Inventor： Ashutosh PANDEY ,  Jay GUPTA ,  Kaushal AGARWAL ,  Justin BENNETT ,  Srinivas Santosh Kumar MADUGULA

IPC: G06F11/10 ,  G06F12/06 ,  G06F12/0882 ,  G06F9/46 ,  G06F9/48 ,  G06F13/40

Abstract: Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.