-
公开(公告)号:US20250156326A1
公开(公告)日:2025-05-15
申请号:US18505952
申请日:2023-11-09
Applicant: NVIDIA CORPORATION
Inventor: Ashutosh PANDEY , Steven E. MOLNAR , Mirko ANDJIC , Amit PABALKAR , Harold W. CAIN, III , Prabal SHARMA
IPC: G06F12/0811 , G06F12/0846 , G06F12/128
Abstract: Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.
-
公开(公告)号:US20210255680A1
公开(公告)日:2021-08-19
申请号:US17306654
申请日:2021-05-03
Applicant: NVIDIA Corporation
Inventor: Sau Yan Keith LI , Thomas E. DEWEY , Arthur CHEN , Simon LAI , Amit PABALKAR , Santosh NAYAK
IPC: G06F1/26 , G06F9/4401 , G06F1/08
Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
-
公开(公告)号:US20200064894A1
公开(公告)日:2020-02-27
申请号:US16108006
申请日:2018-08-21
Applicant: NVIDIA Corporation
Inventor: Sau Yan Keith LI , Thomas E. DEWEY , Arthur CHEN , Simon LAI , Amit PABALKAR , Santosh NAYAK
IPC: G06F1/26 , G06F1/08 , G06F9/4401
Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
-
公开(公告)号:US20250156321A1
公开(公告)日:2025-05-15
申请号:US18506007
申请日:2023-11-09
Applicant: NVIDIA CORPORATION
Inventor: Ashutosh PANDEY , Steven E. MOLNAR , Mirko ANDJIC , Amit PABALKAR , Harold W. CAIN, III , Prabal Sharma
IPC: G06F12/0802
Abstract: Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.
-
-
-