公开(公告)号：US20250156326A1

公开(公告)日：2025-05-15

申请号：US18505952

申请日：2023-11-09

Applicant: NVIDIA CORPORATION

Inventor： Ashutosh PANDEY ,  Steven E. MOLNAR ,  Mirko ANDJIC ,  Amit PABALKAR ,  Harold W. CAIN, III ,  Prabal SHARMA

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/128

Abstract: Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

公开(公告)号：US20140152652A1

公开(公告)日：2014-06-05

申请号：US14082669

申请日：2013-11-18

Applicant: NVIDIA CORPORATION

Inventor： Steven E. MOLNAR ,  Emmett M. KILGARIFF ,  John S. RHOADES ,  Timothy John PURCELL ,  Sean J. TREICHLER ,  Ziyad S. HAKURA ,  Franklin C. CROW ,  James C. BOWMAN

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Abstract translation: 本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。 多个独立的几何单元在不同的图形基元上同时执行几何处理。 原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。 多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

公开(公告)号：US20230315328A1

公开(公告)日：2023-10-05

申请号：US17698409

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Hemayet HOSSAIN ,  Steven E. MOLNAR ,  Jonathon Stuart Ramsay EVANS ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Vyas VENKATARAMAN ,  Mark HAIRGROVE ,  Geoffrey GERFIN ,  Jeffrey M. SMITH ,  Terje BERGSTROM ,  Vikram SETHI ,  Piyush PATEL

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

公开(公告)号：US20170097896A1

公开(公告)日：2017-04-06

申请号：US14874244

申请日：2015-10-02

Applicant: NVIDIA CORPORATION

Inventor： Steven E. MOLNAR ,  James Leroy DEMING ,  Michael A. WOODMANSEE

IPC: G06F12/10 ,  G06F12/06

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to efficiently process requests to access memory that includes protected regions. Upon receiving an initial request via a virtual address (VA), the MMU translates the VA to a physical address (PA) based on page table entries (PTEs) and gates the response based on page-specific secure state information. To thwart software-based attempts to illicitly access the protected regions, the secure state information is not stored in page tables. However, to expedite subsequent requests, after the MMU identifies the PTE and the corresponding secure state information, the MMU stores both the PTE and the secure state information as a cache line in a translation lookaside buffer. Advantageously, the disclosed embodiments protect data in the protected regions from security risks associated with software-based protection schemes without incurring the performance degradation associated with hardware-based “carve-out” memory protection schemes.

公开(公告)号：US20250156321A1

公开(公告)日：2025-05-15

申请号：US18506007

申请日：2023-11-09

Applicant: NVIDIA CORPORATION

Inventor： Ashutosh PANDEY ,  Steven E. MOLNAR ,  Mirko ANDJIC ,  Amit PABALKAR ,  Harold W. CAIN, III ,  Prabal Sharma

IPC: G06F12/0802

Abstract: Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.