公开(公告)号：US20170148203A1

公开(公告)日：2017-05-25

申请号：US14952390

申请日：2015-11-25

Applicant: NVIDIA CORPORATION

Inventor： Ziyad HAKURA ,  Cynthia ALLISON ,  Dale KIRKLAND ,  Jeffrey BOLZ ,  Yury URALSKY ,  Jonah ALBEN

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/50 ,  G06T17/20 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20

Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

公开(公告)号：US20140118381A1

公开(公告)日：2014-05-01

申请号：US14023309

申请日：2013-09-10

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Robert OHANNESSIAN ,  Cynthia ALLISON ,  Dale L. KIRKLAND

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.

Abstract translation: 本发明的一个实施例包括在渲染图像时处理与高速缓存拼贴相关联的图形图元的方法。 从图形处理流水线的第一部分接收与第一渲染目标配置相关联的一组图形基元，并且将该组图形基元存储在存储器中。 检测到指示图形基元集合准备好进行处理的条件，并且选择与该组图形基元中的至少一个图形基元相交的高速缓存片。 与高速缓存片相交的图形基元组中的至少一个图形原语被传送到图形处理流水线的第二部分进行处理。 所公开的实施例的一个优点是图形原语和相关联的数据在高速缓存图块呈现期间更可能保持在芯片上，从而降低功耗并提高渲染性能。

公开(公告)号：US20170148204A1

公开(公告)日：2017-05-25

申请号：US14952400

申请日：2015-11-25

Applicant: NVIDIA CORPORATION

Inventor： Ziyad HAKURA ,  Cynthia ALLISON ,  Dale KIRKLAND ,  Jeffrey BOLZ ,  Yury URALSKY ,  Jonah ALBEN

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/50 ,  G06T17/20 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.