公开(公告)号：US20140232729A1

公开(公告)日：2014-08-21

申请号：US13772182

申请日：2013-02-20

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Dale L. KIRKLAND

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06F9/5022 ,  G06F9/5094 ,  G06T1/60 ,  G06T2210/52 ,  Y02D10/22

Abstract: Attributes of graphics objects are processed in a plurality of graphics processing pipelines. A streaming multiprocessor (SM) retrieves a first set of parameters associated with a set of graphics objects from a first set of buffers. The SM performs a first set of operations on the first set of parameters according to a first phase of processing to produce a second set of parameters stored in a second set of buffers. The SM performs a second set of operations on the second set of parameters according to a second phase of processing to produce a third set of parameters stored in a third set of buffers. One advantage of the disclosed techniques is that work is redistributed from a first phase to a second phase of graphics processing without having to copy the attributes to and retrieve the attributes from the cache or system memory, resulting in reduced power consumption.

Abstract translation: 在多个图形处理流水线中处理图形对象的属性。 流式多处理器（SM）从第一组缓冲器检索与一组图形对象相关联的第一组参数。 SM根据第一处理阶段对第一组参数执行第一组操作，以产生存储在第二组缓冲器中的第二组参数。 SM根据第二处理阶段对第二组参数执行第二组操作，以产生存储在第三组缓冲器中的第三组参数。 所公开技术的一个优点是工作从图形处理的第一阶段到第二阶段重新分配，而不必将属性复制到高速缓存或系统存储器中的属性并从其中检索属性，导致功耗降低。

公开(公告)号：US20140118381A1

公开(公告)日：2014-05-01

申请号：US14023309

申请日：2013-09-10

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Robert OHANNESSIAN ,  Cynthia ALLISON ,  Dale L. KIRKLAND

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.

Abstract translation: 本发明的一个实施例包括在渲染图像时处理与高速缓存拼贴相关联的图形图元的方法。 从图形处理流水线的第一部分接收与第一渲染目标配置相关联的一组图形基元，并且将该组图形基元存储在存储器中。 检测到指示图形基元集合准备好进行处理的条件，并且选择与该组图形基元中的至少一个图形基元相交的高速缓存片。 与高速缓存片相交的图形基元组中的至少一个图形原语被传送到图形处理流水线的第二部分进行处理。 所公开的实施例的一个优点是图形原语和相关联的数据在高速缓存图块呈现期间更可能保持在芯片上，从而降低功耗并提高渲染性能。

公开(公告)号：US20140118380A1

公开(公告)日：2014-05-01

申请号：US14016789

申请日：2013-09-03

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Pierre SOUILLOT ,  Cynthia Ann Edgeworth ALLISON ,  Dale L. KIRKLAND ,  Walter R. STEINER

IPC: G06T1/60

CPC classification number: G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.

Abstract translation: 本发明的一个实施例包括图形子系统，其包括平铺单元，横杆单元和屏幕空间管线。 交叉单元被配置为将与状态改变命令交错的原语发送到平铺单元。 拼接单元被配置为记录与图元相关联的初始状态，并且向屏幕空间流水线发送与第一高速缓存块重叠的图元中的一个或多个图元。 平铺单元还被配置为将初始状态发送到屏幕空间流水线并且向屏幕空间流水线发送与第二高速缓存块重叠的原语中的一个或多个基元。 平铺单元包括状态过滤块，其被配置为确定状态改变命令中的第一状态改变后跟第二状态改变，而没有中间原语，并且放弃发送响应中的第一状态改变。

公开(公告)号：US20150089151A1

公开(公告)日：2015-03-26

申请号：US14037212

申请日：2013-09-25

Applicant: NVIDIA CORPORATION

Inventor： Jeffrey Bolz ,  Patrick R. BROWN ,  Steven J. HEINRICH ,  Dale L. KIRKLAND ,  Joel MCCORMACK

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/1018 ,  G06F12/128 ,  G06F2212/455 ,  Y02D10/13

Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.

Abstract translation: 公开了用于执行存储器访问操作的技术。 纹理单元接收包括与多个视图中的第一视图相关联的元组的存储器访问操作。 纹理单元检索与多个纹理标题中的第一纹理标题相关联的第一散列值，其中第一纹理标题与第一视图相关。 纹理单元检索与多个纹理标题中的第二纹理标题相关联的第二散列值，其中第二纹理标题与第二视图相关。 基于第一和第二哈希值，纹理单元确定第一视图是否与第二视图潜在地别名。 如果是，则纹理单元使与第二纹理头相关联的高速缓冲存储器中的高速缓存条目无效。 否则，纹理单元维护高速缓存条目。

公开(公告)号：US20140184617A1

公开(公告)日：2014-07-03

申请号：US13728881

申请日：2012-12-27

Applicant: NVIDIA CORPORATION

Inventor： Gregory Scott PALMER ,  Ziyad S. HAKURA ,  Emmett M. KILGARIFF ,  Dale L. KIRKLAND ,  Lacky V. SHAH

IPC: G06F9/38

CPC classification number: G06T1/20

Abstract: One embodiment of the present invention sets forth a technique for mid-primitive execution preemption. When preemption is initiated no new instructions are issued, in-flight instructions progress to an execution unit boundary, and the execution state is unloaded from the processing pipeline. The execution units within the processing pipeline, including the coarse rasterization unit complete execution of in-flight instructions and become idle. However, rasterization of a triangle may be preempted at a coarse raster region boundary. The amount of context state to be stored is reduced because the execution units are idle. Preempting at the mid-primitive level during rasterization reduces the time from when preemption is initiated to when another process can execute because the entire triangle is not rasterized.

Abstract translation: 本发明的一个实施例提出了一种用于中原始执行抢占的技术。 当启动抢占时，不会发出新的指令，飞行中的指令进行到执行单位边界，执行状态从处理流水线中卸载。 处理流水线内的执行单元，包括粗略光栅化单元，完成飞行中指令的执行并变为空闲状态。 然而，在粗略的栅格区域边界处，可以抢占三角形的光栅化。 由于执行单元是空闲的，因此减少了要存储的上下文状态量。 在光栅化过程中，在中等原始级别抢占时间减少了从抢占启动到另一个进程可以执行的时间，因为整个三角形不被光栅化。

公开(公告)号：US20140118391A1

公开(公告)日：2014-05-01

申请号：US13967195

申请日：2013-08-14

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Dale L. KIRKLAND

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a method for generating accumulated bounding boxes for graphics primitives. The method includes generating a first bounding box associated with a first graphics primitive. The method further includes, for each graphics primitive included in a first set of one or more additional graphics primitives, determining that the graphics primitive is within a threshold distance of the first bounding box, and adding the graphics primitive to the first bounding box. The method further includes determining not to add a second graphics primitive to the first bounding box. The method further includes generating a second bounding box associated with the second graphics primitive. Finally, the method includes transmitting the first bounding box to a tiling unit via a crossbar. One advantage of the disclosed embodiments is that multiple bounding boxes are combined to generate an accumulated bounding box that is then transferred across the crossbar.

Abstract translation: 本发明的一个实施例包括用于产生用于图形基元的累加边界框的方法。 该方法包括生成与第一图形基元相关联的第一边界框。 该方法还包括对于包括在一个或多个附加图形基元的第一组中的每个图形原语，确定图形基元在第一边界框的阈值距离之内，并且将图形基元添加到第一边界框。 该方法还包括确定不将第二图形基元添加到第一边界框。 该方法还包括生成与第二图形基元相关联的第二边界框。 最后，该方法包括经由横杆将第一边界箱发送到平铺单元。 所公开的实施例的一个优点是组合多个边界框以产生累积的边界框，然后将其跨越横杠传送。

公开(公告)号：US20140118376A1

公开(公告)日：2014-05-01

申请号：US14046856

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Walter R. STEINER ,  Cynthia Ann Edgeworth ALLISON ,  Rouslan DIMITROV ,  Karim M. ABDALLA ,  Dale L. KIRKLAND ,  Emmett M. KILGARIFF

IPC: G09G5/00

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.

Abstract translation: 本发明的一个实施例包括一种在基于瓦片的架构中处理图形基元的技术。 该技术包括在缓冲器中存储从世界空间管道接收的第一多个图形基元和第一多个状态束。 该技术还包括基于第一条件确定第一多个图形基元应该从缓冲器重放，并且作为响应，针对包括在第一多个瓦片中的第一瓦片重播第一多个图形基元。 重放第一多个图形基元包括比较每个图形原语与第一图块以确定图形基元是否与第一图块相交，确定一个或多个图形图元与第一图块相交，以及发送一个或多个图形图元，以及一个或多个图形基元 更多关联的状态束到屏幕空间管线进行处理。

公开(公告)号：US20140118375A1

公开(公告)日：2014-05-01

申请号：US14045372

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Karim M. ABDALLA ,  Ziyad S. HAKURA ,  Cynthia Ann Edgeworth ALLISON ,  Dale L. KIRKLAND

IPC: G09G5/395

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.

Abstract translation: 本发明的一个实施例提出了一种用于在基于瓦片的架构中管理缓冲器表条目的技术。 该技术包括将多个着色器寄存器绑定到缓冲表条目。 该技术还包括通过读取存储在着色器寄存器中的缓冲表索引来访问缓冲表条目，读取存储在缓冲表条目中的缓冲器地址，访问与缓冲器地址相关联的数据，以及解除着色器的绑定来处理至少一个瓦片 从缓冲区表中注册。 该技术还包括确定没有一个着色器寄存器仍然被绑定到缓冲器表条目，并且作为响应，使释放包被插入到指令流中。 该技术还包括确定最后一个瓦片已被处理，并且作为响应，发送释放分组以使释放缓冲器表条目。

公开(公告)号：US20140118373A1

公开(公告)日：2014-05-01

申请号：US14045361

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Cynthia Ann Edgeworth ALLISON ,  Dale L. KIRKLAND ,  Andrei KHODAKOVSKY ,  Jeffrey A. BOLZ

IPC: G09G5/395

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing graphics processing resources in a tile-based architecture. The technique includes storing a release packet associated with a graphics processing resource in a buffer and initiating a replay of graphics primitives stored in the buffer and associated with the graphics processing resource. The technique further includes, for each tile included in a plurality of tiles and processed during the replay, reading the release packet and determining whether the tile is a last tile processed during the replay. The technique further includes determining not to transmit the release packet to a screen-space pipeline and continuing to read graphics data stored in the buffer if the tile is not the last tile to be processed during the replay, or transmitting the release packet to the screen-space pipeline if the tile is the last tile to be processed during the replay.

Abstract translation: 本发明的一个实施例提出了一种用于管理基于瓦片的架构中的图形处理资源的技术。 该技术包括将与图形处理资源相关联的释放分组存储在缓冲器中，并且启动存储在缓冲器中并与图形处理资源相关联的图形基元的重放。 该技术还包括对于包括在多个瓦片中并在重放期间被处理的每个瓦片，读取释放分组并确定瓦片是否是在重放期间处理的最后一个瓦片。 该技术还包括确定不将释放分组发送到屏幕空间流水线，并且如果瓦片不是在重放期间要处理的最后一个瓦片，或者将释放分组发送到屏幕，则继续读取存储在缓冲器中的图形数据 如果瓦片是在重放期间要处理的最后一个瓦片，则为 - 空间管道。

公开(公告)号：US20150097845A1

公开(公告)日：2015-04-09

申请号：US14046850

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Cynthia Ann Edgeworth ALLISON ,  Joseph CAVANAUGH ,  Dale L. KIRKLAND ,  Emmett M. KILGARIFF

IPC: G06F9/38 ,  G06T15/80 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.

Abstract translation: 本发明的一个实施例包括一种在基于瓦片的架构中处理图形基元的技术。 该技术包括在缓冲器中存储从世界空间流水线接收的第一多个图形基元和第一多个状态束，并且将第一多个图形基元发送到屏幕空间管线以进行平铺功能 启用。 该技术还包括在缓冲器中存储从世界空间管道接收的第二多个图形基元和第二多个状态束。 该技术还包括基于第一条件来确定应该禁用平铺函数，并且应该从缓冲器刷新第二多个图形基元，并且将第二多个图形基元发送到屏幕空间管线用于处理 而平铺功能被禁用。