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公开(公告)号：US12001725B2
公开(公告)日：2024-06-04
申请号：US18454693
申请日：2023-08-23
Applicant: NVIDIA Corporation
Inventor： Niladrish Chatterjee , James Michael O'Connor , Donghyuk Lee , Gaurav Uttreja , Wishwesh Anil Gandhi
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F12/0607 , G06F12/10 , G06F2212/151 , G06F2212/154 , G06F2212/657 , H01L25/18
Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.
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公开(公告)号：US11789649B2
公开(公告)日：2023-10-17
申请号：US17237165
申请日：2021-04-22
Applicant: NVIDIA Corporation
Inventor： Niladrish Chatterjee , James Michael O'Connor , Donghyuk Lee , Gaurav Uttreja , Wishwesh Anil Gandhi
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F12/0607 , G06F12/10 , G06F2212/151 , G06F2212/154 , G06F2212/657 , H01L25/18
Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.
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3.发明申请公开(公告)号：US20220374961A1
公开(公告)日：2022-11-24
申请号：US17325116
申请日：2021-05-19
Applicant: NVIDIA CORPORATION
Inventor： Hanrui Wang , James Michael O'Connor , Donghyuk Lee
IPC: G06Q30/06 , G06F16/901 , G06F17/16
Abstract: One embodiment sets forth a technique for performing matrix operations. The technique includes traversing a tree structure to access one or more non-empty regions within a matrix. The tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. The first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. The second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. The technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.
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公开(公告)号：US12141451B2
公开(公告)日：2024-11-12
申请号：US18163167
申请日：2023-02-01
Applicant: NVIDIA Corporation
Abstract: Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.
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公开(公告)号：US20220342595A1
公开(公告)日：2022-10-27
申请号：US17237165
申请日：2021-04-22
Applicant: NVIDIA Corporation
Inventor： Niladrish Chatterjee , James Michael O'Connor , Donghyuk Lee , Gaurav Uttreja , Wishwesh Anil Gandhi
Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.
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Patent Agency Ranking
公开(公告)号：US20240281300A1
公开(公告)日：2024-08-22
申请号：US18528333
申请日：2023-12-04
Applicant: NVIDIA Corporation
Inventor： Donghyuk Lee , Leul Wuletaw Belayneh , Niladrish Chatterjee , James Michael O'Connor
CPC classification number: G06F9/5083 , G06F9/542 , G06F2209/509
Abstract: An initiating processing tile generates an offload request that may include a processing tile ID, source data needed for the computation, program counter, and destination location where the computation result is stored. The offload processing tile may execute the offloaded computation. Alternatively, the offload processing tile may deny the offload request based on congestion criteria. The congestion criteria may include a processing workload measure, whether a resource needed to perform the computation is available, and an offload request buffer fullness. In an embodiment, the denial message that is returned to the initiating processing tile may include the data needed to perform the computation (read from the local memory of the offload processing tile). Returning the data with the denial message results in the same inter-processing tile traffic that would occur if no attempt to offload the computation were initiated.
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公开(公告)号：US20240256153A1
公开(公告)日：2024-08-01
申请号：US18163167
申请日：2023-02-01
Applicant: NVIDIA Corporation
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0644 , G06F3/0659 , G06F3/0673
Abstract: Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.
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公开(公告)号：US20230393788A1
公开(公告)日：2023-12-07
申请号：US18454693
申请日：2023-08-23
Applicant: NVIDIA Corporation
Inventor： Nilandrish Chatterjee , James Michael O'Connor , Donghyuk Lee , Gaurav Uttreja , Wishwesh Anil Gandhi
CPC classification number: G06F3/0659 , G06F3/0604 , G06F12/0607 , G06F12/10 , H01L25/18 , G06F2212/657 , G06F2212/151 , G06F2212/154 , G06F3/0673
Abstract: A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.
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公开(公告)号：US11709812B2
公开(公告)日：2023-07-25
申请号：US17325133
申请日：2021-05-19
Applicant: NVIDIA CORPORATION
Inventor： Hanrui Wang , James Michael O'Connor , Donghyuk Lee
IPC: G06F16/22 , G06F17/16 , G06F18/2134
CPC classification number: G06F16/2237 , G06F16/2246 , G06F16/2272 , G06F17/16 , G06F18/21345
Abstract: One embodiment sets forth a technique for generating a tree structure within a computer memory for storing sparse data. The technique includes dividing a matrix into a first plurality of equally sized regions. The technique also includes dividing at least one region in the first plurality of regions into a second plurality of regions, where the second plurality of regions includes a first region and one or more second regions that have a substantially equal number of nonzero matrix values and are formed within the first region. The technique further includes creating the tree structure within the computer memory by generating a first plurality of nodes representing the first plurality of regions, generating a second plurality of nodes representing the second plurality of regions, and grouping, under a first node representing the first region, one or more second nodes representing the one or more second regions.
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10.发明授权公开(公告)号：US12211080B2
公开(公告)日：2025-01-28
申请号：US17325116
申请日：2021-05-19
Applicant: NVIDIA CORPORATION
Inventor： Hanrui Wang , James Michael O'Connor , Donghyuk Lee
IPC: G06F16/901 , G06F17/16 , G06Q30/0601
Abstract: One embodiment sets forth a technique for performing matrix operations. The technique includes traversing a tree structure to access one or more non-empty regions within a matrix. The tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. The first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. The second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. The technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.
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